Changing the Odds Against Masked Logic

  • Kris Tiri
  • Patrick Schaumont
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4356)


Random switching logic (RSL) has been proposed as an efficient countermeasure to mitigate power analysis. The logic style equalizes the output transition probabilities using a random mask-bit. This manuscript, however, will show a successful attack against RSL. The single mask-bit can only add one bit of entropy to the information content of the overall power consumption variations and can very easily be deduced from the power consumption. Once the mask-bit is known, the a posteriori probabilities of the output transitions are not equal anymore and a power analysis can be mounted. A threshold filter suffices to remove the additional bit of information.


Power Consumption Clock Cycle Logic Gate Output Transition Posteriori Probability 
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  1. 1.
    Chandrakasan, A., Sheng, S., Brodersen, R.: Low Power CMOS Design. IEEE Journal of Solid-State Circuits (JSSC) 27(4), 473–484 (1992)CrossRefGoogle Scholar
  2. 2.
    Mangard, S., Popp, T., Gammel, B.: Side-Channel Leakage of Masked CMOS Gates. In: Menezes, A.J. (ed.) CT-RSA 2005. LNCS, vol. 3376, pp. 351–365. Springer, Heidelberg (2005)Google Scholar
  3. 3.
    Peeters, E., Standaert, F., Donckers, N., Quisquater, J.: Improved Higher Order Side-Channel Attacks with FPGA experiments. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 309–323. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  4. 4.
    Moyer, B.: Low-power design for embedded processors. Proceedings of the IEEE 89(11), 1576–1587 (2001)CrossRefGoogle Scholar
  5. 5.
    Suzuki, D., Saeki, M., Ichikawa, T.: Random Switching Logic: A Countermeasure against DPA based on Transition Probability. Cryptology ePrint Archive, Report 2004/346 (2004)Google Scholar
  6. 6.
    Suzuki, D., Saeki, M., Ichikawa, T.: DPA Leakage Models for CMOS Logic Circuits. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 366–382. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  7. 7.
    Tiri, K., Hwang, D., Hodjat, A., Lai, B., Yang, S., Schaumont, P., Verbauwhede, I.: Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 354–365. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  8. 8.
    Weste, N., Harris, D.: Principles of CMOS VLSI Design, 3rd edn. Addison-Wesley, Reading (2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Kris Tiri
    • 1
  • Patrick Schaumont
    • 2
  1. 1.Trusted Platform Laboratory, Intel CorporationUSA
  2. 2.ECE Department, Virginia TechUSA

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