Abstract
In this paper we present a new static power minimization technique exploiting the use of triple-threshold CMOS standard cell libraries in 90nm technology. Using static timing analysis, we determine the timing requirements of cells and place cells with low and standard threshold voltages in the critical paths. Cells with a high threshold voltage are placed in non-critical paths to minimize the static power with no overall timing degradation. From the timing and power analysis, we determine the optimal placement of high, standard and low threshold voltage cells. Using three different threshold voltages, an optimized triple-threshold 16-bit multiplier design featured 90% less static power compared to the pure low-threshold design and 54% less static power compared to the dual-threshold design.
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Chen, H.I.A., Loo, E.K.W., Kuo, J.B., Syrzycki, M.J. (2007). Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_44
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DOI: https://doi.org/10.1007/978-3-540-74442-9_44
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
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