Abstract
This paper proposes a novel random replacement method in fully or set associative structures such as TLBs to improve the performance of the main or high-priority thread running in an SMT processor along with other low-priority threads. The proposed random replacement technique considers the thread priorities when performing a random selection of evicted entries in the table. The replacement scheme increases the probability of evicting a low-priority thread entry by generating more than one random number index. We have shown that this simple and low-cost random replacement logic can boost the performance of the high-priority thread significantly with only minimal additional hardware support. Our results indicate that generating only 3 random numbers can increase the performance of the high-priority thread by about 9%, and provides the highest overall IPC for an 8-entry data TLB.
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© 2007 Springer-Verlag Berlin Heidelberg
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Özer, E., Biles, S. (2007). Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor. In: Choi, L., Paek, Y., Cho, S. (eds) Advances in Computer Systems Architecture. ACSAC 2007. Lecture Notes in Computer Science, vol 4697. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74309-5_35
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DOI: https://doi.org/10.1007/978-3-540-74309-5_35
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74308-8
Online ISBN: 978-3-540-74309-5
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