Abstract
Efficiency and flexibility are crucial features of processors in the embedded systems. The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. And the flexibility allows design modifications in order to respond to different applications. As the superset of traditional very long instruction word (VLIW) architecture, Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. The main advantages of TTA are its simplicity and flexibility. In TTA processors, the special function units can be utilized to increase performance or reduce power dissipation. In this paper, we design a low-power processor architecture using asynchronous function units based on TTA. The processor core is globally synchronous and locally asynchronous implementation using not only synchronous function units but also asynchronous function units. We solve the problem that use asynchronous circuits in TTA that is only synchronous design environment. The test result shows that this processor has lower power dissipation and higher performance than its pure synchronous version that only uses synchronous function units.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Keutzer, K., Malik, S., Newton, A.R.: From ASIC to ASIP: The next design discontinuity. In: ICCD 2002. Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 84–90 (2002)
Werner, T., Akella, V.: Asynchronous processor survey. Computer 30(11), 67–76 (1997)
Furber, S.B., Garside, J.D., Temple, S., Liu, J., Day, P., Paver, N.C.: AMULET2e: An asynchronous embedded controller. In: Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 290–299 (1997)
Furber, S.B., Edwards, D.A., Garside, J.D.: AMULET3: a 100 MIPS asynchronous embedded processor. In: Proceedings of the 2000 IEEE International Conference on Computer Design, pp. 329–334 (2000)
Garside, J.D., Bainbridge, W.J., Bardsley, A., Clark, D.M., Edwards, D.A., Furber, S.B., Lloyd, D.W., Mohammadi, S., Pepper, J.S., Temple, S., Woods, J.V., Liu, J., Petlin, O.: AMULET3i - an asynchronous System-on-Chip. In: Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 162–175 (2000)
Plana, L.A., Riocreux, P.A., Bainbridge, W.J., Bardsley, A., Garside, J.D., Temple, S.: Spa: A synthesisable amulet core for smartcard pplications. In: Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems, pp. 201–210 (2002)
Garnica, O., Lanchares, J., Hermida, R.: Fine-grain asynchronous circuits for low-power high performance DSP implementations. In: IEEE Workshop on Signal Processing Systems, pp. 519–528 (2000)
Kawokgy, M., Salama, C.A.T.: Low-power asynchronous viterbi decoder for wireless applications. In: Proceedings of the 2004 international symposium on Low power electronics and design, pp. 286–289 (2004)
Corporaal, H.: Microprocessor Architecture: from VLIW to TTA. John Wiley & Sons Ltd, Chichester (1998)
Corporaal, H., Arnold, M.: Using Transport Triggered Architectures for embedded processor design. Integrated Computer-Aided Engineering 5(1), 19–37 (1998)
Weste, N.H.E., Eshraghian, K.: Principles of CMOS VLSI design: a systems perspective. Addison-Wesley Longman Publishing Co., Inc, Boston, MA, USA (1985)
Chandrakasan, A., Sheng, S., Brodersen, R.: Low-power CMOS digital design. IEEE Journal of Solid-State Circuits 27(4), 473–484 (1992)
Pitkanen, T., Makinen, R., Heikkinen, J., Partanen, T., Takala, J.: Low–power, high–performance tta processor for 1024–point fast fourier transform. In: Int. Workshop SAMOS, pp. 227–236 (2006)
Nielsen, L.S.: Low-power Asynchronous VLSI Design. PhD thesis, Technical University of Denmark, Department of Information Technology (1997)
Yue, H., Lai, M.C., Dai, K., Wang, Z.Y.: Design of a configurable embedded processor architecture for dsp functions. In: ICPADS’05. Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops, vol. 02, pp. 27–31 (2005)
Sutherland, I.E.: Micropipelines. Communications of the ACM 32(6), 720–738 (1998)
Piguet, C., Zahnd, J.: STG-based synthesis of speed-independent CMOS cells. In: Workshop on Exploitation of STG-Based Design Technology (1998)
Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Transactions on Information and Systems E80-D(3), 315–325 (1997)
Li, Y., Wang, L., Gong, R., Dai, K., Wang, Z.Y.: Research and implementation of a 32-bit asynchronous multiplier. Computer Research and Development 43(12), 2152–2157 (2006)
Zhou, Y., Sokolov, D., Yakovlev, A.: Cost-aware synthesis of asynchronous circuits based on partial acknowledgement. In: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pp. 158–163 (2006)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Li, Y., Wang, Z., Zhao, X., Ruan, J., Dai, K. (2007). Design of a Low–Power Embedded Processor Architecture Using Asynchronous Function Units. In: Choi, L., Paek, Y., Cho, S. (eds) Advances in Computer Systems Architecture. ACSAC 2007. Lecture Notes in Computer Science, vol 4697. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74309-5_33
Download citation
DOI: https://doi.org/10.1007/978-3-540-74309-5_33
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74308-8
Online ISBN: 978-3-540-74309-5
eBook Packages: Computer ScienceComputer Science (R0)