Leakage Energy Reduction in Cache Memory by Software Self-invalidation

Abstract

Recently, energy dissipation by microprocessors is getting larger, which leads to a serious problem in terms of allowable temperature and performance improvement for future microprocessors. Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory, and has increased in its size. However, energy dissipation in the cache memory will approach or exceed 50% of the increasing total dissipation by processors. An important point to note is that, in the near future, static (leakage) energy will dominate the total energy consumption in deep sub-micron processes. In this paper, we propose cache memory architecture, especially for on-chip multiprocessors, that achieves efficient reduction of leakage energy in cache memories by exploiting gated-Vdd control and software self-invalidation. In the simulation, our technique reduced 46.5% of leakage energy at maximum, and 23.4% on average, in the execution of SPLASH-2 programs.