Abstract
In this paper, we propose the first interrelated power and latency mathematical model for the Networks-on-Chip (NoC) architecture with mesh topology. Through an analytical approach, we show the importance of tile selection in which the hot (frequently accessed) IP core is mapped. Taking into account the effect of blocking in both power and latency models, causes the estimated values to be more accurate. Simulation results confirm the reasonable accuracy of the proposed model. The major output of the model which is the average energy consumption per cycle in the whole network is the efficacious parameter that is most important and must be used by NoC designers.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Chandrakasan, A., Brodersen, R.: Minimizing power consumption in digital CMOS circuits. Proc. IEEE 83, 498–523 (1995)
Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low power CMOS digital design. IEEE J. Solid-State Circuits 27, 473–484 (1992)
Hu, J., Marculescu, R.: Energy-aware mapping for Tile-based NOC architectures under performance constraints. Design Automation (2003)
Hu, J., Marculescu, R.: Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures. Design Automation, and Test 1 (2004)
Murali, S., De Micheli, G.: Bandwidth-constrained mapping of cores onto NoC architectures. Design, Automation and Test 2, 896–901 (2004)
Lei, T., Kumar, S.: A two-step genetic algorithm for mapping task graphs to a network on chip architecture. Digital System Design, 180–187 (2003)
Wang, H.-S., Zhu, X., Peh, L.-S., Malik, S.: Orion: A power-performance simulator for interconnection networks. Microarchitecture, 294–305 (2002)
Wang, H.-S., Peh, L.-S., Malik, S.: Power-driven design of router microarchitectures in on-chip networks. Microarchitecture, 105–116 (2003)
Chien, A.A.: A cost and performance model for k-ary n-cubes wormhole routers. IEEE Trans. Parallel and Distributed Systems 9, 150–162 (1998)
Wang, H.S., Peh, L.S., Malik, S.: A power model for routers: modeling Alpha 21364 and InfiniBand routers. High Performance Interconnects, 21–27 (2002)
Mamidipaka, M., Khouri, K., Dutt, N., Abadir, M.: Leakage power estimation in SRAMs. CECS Technical Report, Center for Embedded Computing Systems, University of California, Irvine, CA (2003)
Draper, J.T., Ghosh, J.: A comprehensive analytical model for wormhole routing in multicomputer systems. J. Parallel and Distributed Computing 23, 202–214 (1994)
Sarbazi-azad, H., Ould-Khaoua, M., Mackenzie, L.M.: Analytical modeling of wormhole-routed k-ary n-cubes in the presence of hot-spot traffic. IEEE Trans. Parallel and Distributed Systems 50, 623–634 (2001)
Sarbazi-azad, H.: Performance analysis of wormhole routing in multicomputer interconnection networks. PhD Thesis, University of Glasgow, Glasgow, UK (2002)
Dally, W.J.: Virtual channel flow control. IEEE Trans. Parallel and Distributed Systems 3, 194–205 (1992)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Moraveji, R., Sarbazi-Azad, H., Abbaspour, M. (2007). Optimal Placement of Frequently Accessed IPs in Mesh NoCs. In: Choi, L., Paek, Y., Cho, S. (eds) Advances in Computer Systems Architecture. ACSAC 2007. Lecture Notes in Computer Science, vol 4697. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74309-5_14
Download citation
DOI: https://doi.org/10.1007/978-3-540-74309-5_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74308-8
Online ISBN: 978-3-540-74309-5
eBook Packages: Computer ScienceComputer Science (R0)