Abstract
This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.
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Flatt, H., Hesselbarth, S., Flügel, S., Pirsch, P. (2007). A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing . In: Vassiliadis, S., Bereković, M., Hämäläinen, T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2007. Lecture Notes in Computer Science, vol 4599. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73625-7_26
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DOI: https://doi.org/10.1007/978-3-540-73625-7_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73622-6
Online ISBN: 978-3-540-73625-7
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