Abstract
A novel embedded processor element basing on the Transport Triggered Architecture is presented in this paper. The processor element consisting of two powerful arithmetic clusters using the application specific instruction processor design methodology achieves higher performance and is especially good at exploiting the instruction level and data level parallelisms in the multimedia applications. To improve the efficiency, the processor also presents the decoupled stream memory system with the characteristics of the stream buffer proxy to support the cross-line indexed accesses and to enhance the memory bandwidth. Then, a heterogeneous multiprocessor SoC chip involving the embedded processor is fabricated using 0.13um CMOS process, and the SoC operates at 400MHz and consumes only around 690mW. Experimental results show that the embedded processor element has good performance improvement for the multimedia applications.
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References
Corbal, J., et al.: DLP+TLP processors for the next generation of multimedia workload. In: Proc. 7th Intl. Symp. on HPCA (2001)
TMS320C64 DSP library programmer’s reference, Texas Instruments, USA (2003)
Corporaal, H., Janssen, J., Arnold, M.: Computation in the Context of Transport Triggered Architectures. International Journal of Parallel Programming 28(4), 401–427 (2000)
Dr.Gordon Cichon.: Introduction into Synchronous Transfer Architecture (STA) (February 2005)
Hong, Y., Li, S., Kui, D., Zhiying, W.: A TTA-based ASIP design methodology for embedded systems. The Journal of the Computer Research and Development, 752–758 (2006)
Hoogerbrugge, J., Corporaal, H.: Transport-triggering vs. operation-triggering. In: Compiler Construction conference CC-94 (1994)
Kapasi, U.J., Dally, W.J., Rixner, S.: Efficient Conditional Operations for Data-parallel Architectures. In: Proc. Intl. Symp. on. Microarchitecture, pp.159–170 (December 2000)
Jayasena, N., Erez, M., Ahn, J.H., Dally, W.J.: Stream Register Files with Indexed Access. In: Tenth International Symposium on High Performance Computer Architecture, February 2004, Madrid, Spain (2004)
Lopez-Lagunas, A., Chai, S.M.: Compiler Manipulation of Stream Descriptors for Data Access Optimization. In: Proceedings of the International Conference Workshops on Parallel Processing, January 2006, pp. 337–344 (2006)
Corporaal, H., Hoogerbrugge, J.: Code generation for Transport Triggered Architectures. In: Code Generation for Embedded Processors, Kluwer Academic Publishers, Boston, MA (1995)
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Mingche, L., Jianjun, G., Yasuai, L., Kui, D., Zhiying, W. (2007). The Research of an Embedded Processor Element for Multimedia Domain. In: Sebe, N., Liu, Y., Zhuang, Y., Huang, T.S. (eds) Multimedia Content Analysis and Mining. MCAM 2007. Lecture Notes in Computer Science, vol 4577. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73417-8_34
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DOI: https://doi.org/10.1007/978-3-540-73417-8_34
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73416-1
Online ISBN: 978-3-540-73417-8
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