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THIN: A New Hierarchical Interconnection Network-on-Chip for SOC

  • Baojun Qiao
  • Feng Shi
  • Weixing Ji
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4494)

Abstract

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip (SOC) designs. A new chip design paradigm called Network-on-Chip (NOC) offers a promising architectural choice for future SOC. Focusing on decreasing node degree, reducing links and shortening diameter, a new NOC, named Triple-based Hierarchical Interconnection Network (THIN), is presented in this paper. The topology of THIN is very simple and it has obviously hierarchical, symmetric and scalable characteristic. The network properties and zero-load latency were studied and compared with 2-D mesh and Hypercube. The results show THIN is superior to 2-D mesh and Hypercube to construct interconnection network for SOC, when the network size is not very large. A new tree-based multicast routing algorithm in THIN is proposed. Thorough analyses and experiments based on different multicast implementation schemes are conducted. The results do confirm the advantage of our scheme over unicast-based and path-based multicast schemes.

Keywords

System-on-Chip Network-on-Chip network topology multicast 

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References

  1. 1.
    Guerrier, P., Greiner, A.: A Generic Architecture for On-Chip Packet-Switched Interconnections. DATE’2000, pp. 250–256. IEEE Press, Piscataway (2000)Google Scholar
  2. 2.
    Benini, L., De Micheli, G.: Networks on Chips: a New SOC Paradigm. IEEE Computer 6, 70–78 (2002)Google Scholar
  3. 3.
    IBM CoreConnect Bus Architecture. [online]. Accessed:January 20th (2006), http://www-03.ibm.com/chips/products/coreconnect/index.html
  4. 4.
    ARM AMBA. [online]. Accessed, May 13 (2005), http://www.arm.com/products/solutions/AMBAHomePage.html
  5. 5.
    Dally, W. J., Towles, B.: Route Packets, not Wires: On-Chip Interconnection Networks. In: Proc. of the 38th Design Automation Conf. Las Vegas, NV, vol. 6, pp. 681–689 (2001)Google Scholar
  6. 6.
    Kumar, S., Jantsch, A., et al.: A Network on Chip Architecture and Design Methodology. In: Proc. of IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, Pennsylvania, USA, vol. 3, pp. 117–124 (2002)Google Scholar
  7. 7.
    Zeferino, C. A., Kreutz, M. E., Carro, L., et al.: A Study of Communication Issues for Systems-on-Chip. In: Proc. of 15th Symposium on Integrated Circuits and Systems Design, Porto Alegre, Brazil, vol. 9, pp. 121–126 (2002)Google Scholar
  8. 8.
    Wiklund, D., Liu, D.: Design of a System-on-Chip Switched Network and its Design Support. In: IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, Vol. 2, Chengdu, China, vol. 6, pp. 1279–1283 (2002)Google Scholar
  9. 9.
    Vecchia, G.D., Sanges, C.: A Recursively Scalable Network VLSI Implementation. Future Generation Computer Systems 4(3), 235–243 (1988)CrossRefGoogle Scholar
  10. 10.
    Fu, J-S.: Hamiltonian-Connectedness of the WK-Recursive Network. In: Proc. of 7th International Symposium on Parallel, Architectures, Algorithms and Networks, Hong Kong, China, vol. 5, pp. 569–574 (2004)Google Scholar
  11. 11.
    Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks: an Engineering Approach. Publishing House of Electronics Industry, Beijing (2004)Google Scholar
  12. 12.
    Dong, Y.-f., Wang, D.-x., Zheng, W.-m.: Exact Computation of the Mean Minimal Path Length of N-Mesh and N-Torus. Chinese Journal of Computers 20(4), 376–380 (1997)Google Scholar
  13. 13.
    Gao. P.: Research on Interconnection Networks of Parallel Signal Processor [Ph. D. dissertation], Harbin Engineering University, Harbin China (2004)Google Scholar
  14. 14.
    Xu, H., McKinley, P.K., Ni, L.M.: Efficient Implementation of Barrier Synchronization in Wormhole-Routed Hypercubes Multicomputers. Journal of Parallel and Distributed Computing 16, 172–184 (1992)CrossRefGoogle Scholar
  15. 15.
    Li, K., Schaefer, R.: A Hypercube Shared Virtual Memory. In: Proceeding of the 1989 International Conference on Parallel Processing, vol. 1, pp. 125–132 (1989)Google Scholar
  16. 16.
    Lin, X., Ni, L.M.: Multicast Communication in Multicomputer Networks. IEEE Transaction on Parallel and Distributed Systems 4(10), 1105–1117 (1993)CrossRefGoogle Scholar
  17. 17.
    Dandamudi, S.P., Eager, D.L.: Hierarchical Interconnection Networks for Multicomputer Systems. IEEE Transactions on Computers 39(6), 786–797 (1990)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Baojun Qiao
    • 1
    • 2
  • Feng Shi
    • 1
  • Weixing Ji
    • 1
  1. 1.School of Computer Science and Technology, Beijing Institute of Technology, 100081 BeijingChina
  2. 2.Institute of Data and Knowledge Engineering, Henan University, 475001 Kaifeng, HenanChina

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