Skip to main content

A Parallel Architecture for Motion Estimation and DCT Computation in MPEG-2 Encoder

  • Conference paper
Algorithms and Architectures for Parallel Processing (ICA3PP 2007)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4494))

  • 540 Accesses

Abstract

This paper presents a parallel architecture that can simultaneously perform block-matching motion estimation (ME) and discrete cosine transform (DCT). Because DCT and ME are both processed block by block, it is preferable to put them in one module for resource sharing. Simulation results performed using Simulink demonstrate that the parallel fashioned architecture improves the performance in terms of running time by 18.6% compared to the conventional sequential fashioned architecture.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Haskell, B.: An introduction to MPEG-2. Chapman & Hall, Sydney (1996)

    Google Scholar 

  2. Ahemd, N., Natarajan, T., Rao, K.R.: Discrete cosine transform. IEEE Trans. Computers C-23, 90–93 (1974)

    Article  Google Scholar 

  3. Guttag, K., Gove, R.J., Van Aken, J.R.: A single chip multiprocessor for multimedia: The mvp. IEEE Computer Graphics and Applications, pp. 53–64 (1992)

    Google Scholar 

  4. Shengqi, Y., Wayne, W., Vijaykrishnan, N.: Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. IEEE Transactions on Computers 54, 714–726 (2005)

    Article  Google Scholar 

  5. Li, R., Zeng, B., Liou, M.L.: A New Three-Step Search Algorithm for Block Motion Estimation. IEEE Transactions on Circuit and System for Video Technology 4, 438–442 (1994)

    Article  Google Scholar 

  6. Po, L.M., Ma, W.C.: A Novel Four-Step Search Algorithm for Fast Block Motion Estimation. IEEE Transactions on Circuit and System for Video Technology 6, 313–317 (1996)

    Article  Google Scholar 

  7. Liu, B., Zaccarin, A.: New Fast Algorithms for the Estimation of Block Motion Vectors. IEEE Transactions on Circuit and System for Video Technology 3, 148–157 (1993)

    Article  Google Scholar 

  8. Chen, W., Smith, C.H., Fralick, S.: A fast computation algorithm for the discrete cosine transform. IEEE Transactions on communications 25, 1004–1009 (1977)

    Article  MATH  Google Scholar 

  9. Lee, Y.P., et al.: A cost effective architecture for 8*8 two-dimensional DCT/IDCT using direct method. IEEE Transactions on Circuit and system for video technology 7, 459–467 (1997)

    Article  Google Scholar 

  10. Loeffler, C., Lightenberg, A., Moschytz, G.S.: Practical fast 1-D DCT algorithm with 11 multiplications. In: Proceedings of ICASSP, vol. 2, pp. 988–991 (1989)

    Google Scholar 

  11. Kung, S.Y.: VLSI Array Processors. Prentice-Hall, Englewood Cliffs (1998)

    Google Scholar 

  12. Nam, S.H., Baek, J.S., Lee, M.K.: Flexible VLSI architecture of full search motion estimation for video applications. IEEE Transactions on Consumer Electronics 40, 176–184 (1994)

    Article  Google Scholar 

  13. Eric, C., Sethuraman, P.: Motion Estimation Architecture for Video Compression. IEEE Transactions on Consumer Electronics 39, 292–297 (1993)

    Article  Google Scholar 

  14. Jiang, M., Luo, Y., Fu, Y.L., Yang, B., Zhao, B.Y.: A low power 1D-DCT Processor for MPEG-targeted Real-time Applications. International Symposium on Communications and Information Technologies, pp. 682–687 (2004)

    Google Scholar 

  15. Nam, J., Choi, T.S.: A Fast Full-Search Motion-Estimation Algorithm Using Representative Pixels and Adaptive Matching Scan. IEEE Transactions on Circuits and Systems for Video Technology 10, 1040–1048 (2000)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Hai Jin Omer F. Rana Yi Pan Viktor K. Prasanna

Rights and permissions

Reprints and permissions

Copyright information

© 2007 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Huang, J., Li, H. (2007). A Parallel Architecture for Motion Estimation and DCT Computation in MPEG-2 Encoder. In: Jin, H., Rana, O.F., Pan, Y., Prasanna, V.K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2007. Lecture Notes in Computer Science, vol 4494. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72905-1_19

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-72905-1_19

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-72904-4

  • Online ISBN: 978-3-540-72905-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics