Abstract
There are only three real “dimensions” to processor performance increases beyond Moore’s law: clock frequency, superscalar instruction issue, and multiprocessing. The first two have been pushed to their logical limits and we must focus on multiprocessing. SMT (simultaneous multithreading) [2] and CMP(chip multiprocessing) [1] are two architectural approaches to exploit thread-level parallelism using available on-chip resources. SMT processors execute instructions from different threads in the same cycle, which has the unique ability to exploit ILP(instruction-level parallelism) and TLP(thread-level parallelism) simultaneously. EPIC(explicitly parallel instruction computing) emphasizes importance of the synergy between compiler and hardware. In this paper, we present our efforts to design and implement a parallel environment, which includes an optimizing, portable parallel compiler OpenUH and SMT architecture EDSMT based on IA-64. The performance is evaluated using the NAS parallel benchmarks.
This work was supported by “63” project No. 2002AA110020, Chinese NSF No. 60376018, No. 60273069 and No. 90207011.
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Deng, Q., Zhang, M., Jiang, J. (2007). A Parallel Infrastructure on Dynamic EPIC SMT. In: Jin, H., Rana, O.F., Pan, Y., Prasanna, V.K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2007. Lecture Notes in Computer Science, vol 4494. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72905-1_15
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