A Parallel Infrastructure on Dynamic EPIC SMT

  • Qingying Deng
  • Minxuan Zhang
  • Jiang Jiang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4494)


There are only three real “dimensions” to processor performance increases beyond Moore’s law: clock frequency, superscalar instruction issue, and multiprocessing. The first two have been pushed to their logical limits and we must focus on multiprocessing. SMT (simultaneous multithreading) [2] and CMP(chip multiprocessing) [1] are two architectural approaches to exploit thread-level parallelism using available on-chip resources. SMT processors execute instructions from different threads in the same cycle, which has the unique ability to exploit ILP(instruction-level parallelism) and TLP(thread-level parallelism) simultaneously. EPIC(explicitly parallel instruction computing) emphasizes importance of the synergy between compiler and hardware. In this paper, we present our efforts to design and implement a parallel environment, which includes an optimizing, portable parallel compiler OpenUH and SMT architecture EDSMT based on IA-64. The performance is evaluated using the NAS parallel benchmarks.


Branch Prediction Parallel Programming Model OpenMP Directive Instruction Window Multithreaded Code 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Qingying Deng
    • 1
  • Minxuan Zhang
    • 1
  • Jiang Jiang
    • 1
  1. 1.College of Computer, National University of Defense, Technology, Changsha 410073, HunanP.R. China

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