Abstract
In this paper an efficient cooperative design framework is proposed to help SOC designers to construct their desired application-specific communication architectures. The proposed framework makes contributions as follows: (1) it outlines an approach of model refinement from one level of abstraction down to another closer to implementation; (2) it is particularly suitable for complex systems which consist of hundreds of processing elements (PEs) because it adopts a “divide-and-conquer” approach and provides the On-Chip Communication Architecture constructing method for PEs with compatible and incompatible protocols; (3) it can achieve a fine trade-off between system performance and implementation cost through a multi-objectives cost function taking into account of bus widths, bus load, cost for arbitration logic and transducers. The correctness and effectiveness of the method is evaluated through an illustrative JPEG decoder application.
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Niu, Y., Bian, J., Wang, H., Tong, K. (2007). An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design. In: Shen, W., Luo, J., Lin, Z., Barthès, JP.A., Hao, Q. (eds) Computer Supported Cooperative Work in Design III. CSCWD 2006. Lecture Notes in Computer Science, vol 4402. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72863-4_13
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DOI: https://doi.org/10.1007/978-3-540-72863-4_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-72862-7
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