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Memory Offset Assignment for DSPs

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Embedded Software and Systems (ICESS 2007)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 4523))

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Abstract

Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimization technique has been given more attention, on-chip instruction memory optimization should not be neglected. We propose in this paper some algorithms for a memory offset assignment for embedded DSP processors in order to minimize the number of instructions for address register operations. Extensive experimental results demonstrate the efficacy of our solution.

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References

  1. Araujo, G.: Code Generation Algorithms for Digital Signal Processors. PhD thesis, Princeton Department of EE (June 1997)

    Google Scholar 

  2. Araujo, G., Malik, S., Lee, M.: Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. In: Proceedings of 33rd ACM/IEEE Design Automation Conference, June 1996, pp. 591–596 (1996)

    Google Scholar 

  3. Araujo, G., Sudarsanam, A., Malik, S.: Instruction Set Design and Optimization for Address Computation in DSP Architectures. In: Proceedings of the 9th International Symposium on System Synthesis, November 1997, pp. 31–37 (1997)

    Google Scholar 

  4. Atri, S., Ramanujam, J., Kandemir, M.T.: Improving offset assignment on embedded processors using transformations. In: Prasanna, V.K., Vajapeyam, S., Valero, M. (eds.) HiPC 2000. LNCS, vol. 1970, pp. 367–374. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  5. Atri, S., Ramanujam, J., Kandemir, M.T.: Improving offset assignment for embedded processors. In: Midkiff, S.P., Moreira, J.E., Gupta, M., Chatterjee, S., Ferrante, J., Prins, J.F., Pugh, B., Tseng, C.-W. (eds.) LCPC 2000. LNCS, vol. 2017, pp. 158–172. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  6. Bartley, D.: Optimization Stack Frame Accesses for Processors with Restricted Addressing Modes. Software Practice and Experience 22(2), 101–110 (1992)

    Article  Google Scholar 

  7. Choi, Y., Kim, T.: Address assignment combined with scheduling in DSP code generation. In: Proc. 39th Design Automation Conference, (June 2002)

    Google Scholar 

  8. Liao, S.: Code Generation and Optimization for Embedded Digital Signal Processors. PhD thesis, MIT Department of EECS (January 1996)

    Google Scholar 

  9. Liao, S., et al.: Storage Assignment to Decrease Code Size. In: Proceedings of the ACM SIGPLAN ’95 Conference on Programming Language Design and Implementation, pp. 186–196 (1995), This is a preliminary version of: Liao, S., Devadas, S., Keutzer, K., Tjiang, S., Wang, A.: Storage assignment to decrease code size. ACM Transactions on Programming Languages and Systems 18(3), 235–253 (1996)

    Google Scholar 

  10. Liao, S., Devadas, S., Keutzer, K., Tjiang, S., Wang, A.: Storage assignment to decrease code size. ACM Transactions on Programming Languages and Systems 18(3), 235–253 (1996)

    Article  Google Scholar 

  11. Leupers, R., Marwedel, P.: Algorithms for Address Assignment in DSP Code Generation. In: Proceedings of International Conference on Computer-Aided Design, pp. 109–112 (1996)

    Google Scholar 

  12. Ramanujam, J., Hong, J., Kandemir, M., Atri, S.: Address register-oriented optimizations for embedded processors. In: Proc. 9th Workshop on Compilers for Parallel Computers (CPC 2001), Edinburgh, Scotland, June 2001, pp. 281–290 (2001)

    Google Scholar 

  13. Rao, A., Pande, S.: Storage Assignment Optimizations to Generate Compact and Efficient Code on Embedded Dsps. In: SIGPLAN ’99, Atlanta, GA, USA, May 1999, pp. 128–138 (1999)

    Google Scholar 

  14. Sudarsanam, A., Malik, S.: Memory Bank and Register Allocation in Software Synthesis for ASIPs. In: Proceedings of International Conference on Computer Aided Design, pp. 388–392 (1995)

    Google Scholar 

  15. Press, W.H., Teukolsky, S.A., Vetterling, W.T., Flannery, B.P. (eds.): Numerical Recipes in C: The Art of Science Computing, pp. 152–155. Cambridge University Press, Cambridge (1993)

    Google Scholar 

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Yann-Hang Lee Heung-Nam Kim Jong Kim Yongwan Park Laurence T. Yang Sung Won Kim

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© 2007 Springer Berlin Heidelberg

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Hong, J., Ramanujam, J. (2007). Memory Offset Assignment for DSPs. In: Lee, YH., Kim, HN., Kim, J., Park, Y., Yang, L.T., Kim, S.W. (eds) Embedded Software and Systems. ICESS 2007. Lecture Notes in Computer Science, vol 4523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72685-2_8

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  • DOI: https://doi.org/10.1007/978-3-540-72685-2_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-72684-5

  • Online ISBN: 978-3-540-72685-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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