Abstract
In an embedded system including a base processor integrated with a tightly coupled accelerator, extracting frequently executed portions of the code (hot portion) and executing their corresponding data flow graph (DFG) on the accelerator brings about more speedup. In this paper, we intend to present our motivations for handling control instructions in DFGs and extending them to Control DFGs (CDFGs). In addition, basic requirements for an accelerator with conditional execution support are proposed. Moreover, some algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural specifications. To show the effectiveness of the proposed ideas, we applied them to the accelerator of an extensible processor called AMBER. Experimental results represent the effectiveness of covering control instructions and using CDFGs versus DFGs.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Auguin, M., Bianco, L., Capella, L., Gresset, E.: Partitioning conditional data flow graphs for embedded system design. In: Proc. of ASAP 2000, pp. 339–348 (2000)
Carrillo, J.E., Chow, P.: The effect of reconfigurable units in superscalar processors. In: Proc. of the ACM/SIGDA FPGA, pp. 141–150 (2001)
Clark, N., Blome, J., Chu, M., Mahlke, S., Biles, S., Flautner, K.: An architecture framework for transparent instruction set customization in embedded processors. In: Proc. ISCA, pp. 272–283 (2005)
Clark, N., Zhong, H., Mahlke, S.: Processor acceleration through automated instruction set customization. In: MICRO-36 (2003)
Hauck, S., Fry, T., Hosler, M., Kao, J.: The Chimaera reconfigurable functional unit. In: IEEE Symp. on FPGAs for Custom Computing Machines, pp. 206–217 (1997)
Karthikeya, M., Gajjala, P., Bhatia, D.: Temporal partitioning and scheduling data flow graphs for reconfigurable computers. IEEE Transactions on Computers 48(6), 579–590 (1999)
Kastner, R., Kaplan, A., Sarrafzadeh, M.: Synthesis techniques and optimizations for reconfigurable systems. Kluwer Academic Publishers, Dordrecht (2004)
Lee, J.E., Kim, Y., Jung, J., Choi, K.: Reconfigurable ALU array architecture with conditional execution. In: International SoC Design Conference, pp. 222–226 (2004)
Lodi, A., Toma, M., Campi, F., Cappelli, A., Canegallo, R., Guerrieri, R.: A VLIW processor with reconfigurable instruction set for embedded applications. IEEE Journal of Solid-State Circuits 38(11), 1876–1886 (2003)
Mahlke, S.A., Hank, R.E., McCormick, J.E., August, D.I., Hwu, W.W.: A comparison of full and partial predicated execution support for ILP processors. In: Proc. ISCA, pp. 138–150 (1995)
Mehdipour, F., Noori, H., Zamani, M.S., Murakami, K., Inoue, K., Sedighi, M.: Custom instruction generation using temporal partitioning techniques for a reconfigurable functional unit. In: Sha, E., Han, S.-K., Xu, C.-Z., Kim, M.-H., Yang, L.T., Xiao, B. (eds.) EUC 2006. LNCS, vol. 4096, pp. 722–731. Springer, Heidelberg (2006)
Mehdipour, F., Saheb Zamani, M., Sedighi, M.: An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. Int. J. of Microprocessors and Microsystems 30(1), 52–62 (2006)
Mei, B., Vernalde, S., Verkest, D., Lauwereins, R.: Design methodology for a tightly coupled VLIW/Reconfigurable matrix architecture. In: DATE, pp. 1224–1229 (2004)
Mibench, http://www.eecs.umich.edu/mibench
Noori, H., Mehdipour, F., Murakami, K., Inoue, K., Saheb Zamani, M.: A reconfigurable functional unit for an adaptive dynamic extensible processor. In: Proc. of IEEE International Conference on Field Programmable Logic and Applications, pp. 781–784 (2006)
Park, J.C., Schlansker, M.S.: On predicated execution. Technical Report HPL-91-58. Hewlett Packard Laboratories (1991)
Razdan, R., Smith, M.D.: A high-performance microarchitecture with hardware-programmable functional units. In: MICRO-27 (1994)
Simplescalar, http://www.simplescalar.com
Smith, J.E., Sohi, G.S.: The microarchitecture of superscalar P. Proc. IEEE 83, 1609–1624 (1995)
Synopsys Inc., http://www.synopsys.com/products/logic/design_compiler.html
Vassiliadis, S., Gaydadjiev, G., Kuzmanov, G.: The MOLEN polymorphic processor. IEEE Transactions on Computers 53(11), 1363–1375 (2004)
Yu, P., Mitra, T.: Characterizing embedded applications for instruction-set extensible processors. In: Proc. Design Automation Conference, pp. 723–728 (2004)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer Berlin Heidelberg
About this paper
Cite this paper
Noori, H., Mehdipour, F., Zamani, M.S., Inoue, K., Murakami, K. (2007). Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. In: Lee, YH., Kim, HN., Kim, J., Park, Y., Yang, L.T., Kim, S.W. (eds) Embedded Software and Systems. ICESS 2007. Lecture Notes in Computer Science, vol 4523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72685-2_24
Download citation
DOI: https://doi.org/10.1007/978-3-540-72685-2_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-72684-5
Online ISBN: 978-3-540-72685-2
eBook Packages: Computer ScienceComputer Science (R0)