Abstract
In this paper, we propose a novel compressed cache hierarchy that uses a unified compression algorithm in both L1 data cache and L2 cache, called Simple Frequent Pattern Compression(S-FPC). This scheme can increase the cache capacity of L1 data cache and L2 cache without any sacrifice of the L1 cache access latency. The layout of compressed data in L1 data cache enables partial cache line prefetching and does not introduce prefetch buffers or increase cache pollution and memory traffic. Compared to a baseline cache hierarchy not supporting data compression in cache, on average, our cache hierarchy design increases the average L1 cache capacity(in terms of the average number of valid words in cache per cycle) by about 33%, reduces the data cache miss rate by 21%, and speeds up program execution by 13%.
This work was supported by National Natural Science Foundation of China, grant No. 60376018.
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Tian, X., Zhang, M. (2007). A Unified Compressed Cache Hierarchy Using Simple Frequent Pattern Compression and Partial Cache Line Prefetching. In: Lee, YH., Kim, HN., Kim, J., Park, Y., Yang, L.T., Kim, S.W. (eds) Embedded Software and Systems. ICESS 2007. Lecture Notes in Computer Science, vol 4523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72685-2_14
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DOI: https://doi.org/10.1007/978-3-540-72685-2_14
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