Abstract
In a sensor network, exploiting the correlation among different sources allows a significant reduction of the transmitted energy at the cost of a complex decoder scheme. This paper introduces the first hardware implementation for joint source-channel decoding of correlated sources. Specifically, a dual-clustered VLIW processor with a highly optimized datapath is presented.
This work was funded by the projects OPTIMA (TEC2006-00739) and MIMESIS (TEC2004-06451-C05-04/TCM) of the Spanish Ministry of Education and Science and TECMAR (IBA/PI2004-3) of the Basque Government Ministry of Industry.
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Ituero, P. et al. (2007). Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. In: Lee, YH., Kim, HN., Kim, J., Park, Y., Yang, L.T., Kim, S.W. (eds) Embedded Software and Systems. ICESS 2007. Lecture Notes in Computer Science, vol 4523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72685-2_10
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DOI: https://doi.org/10.1007/978-3-540-72685-2_10
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