Microprocessor Design

Abstract

When you think of current microprocessors (μPs), the Intel Itanium processor with 592 million transistors may come to mind. Designing this kind of microprocessor with an FPGA, you may ask? Now the author has become overconfident with the capabilities of today’s FPGAs. Clearly today’s FPGAs will not be able to implement such a top-of-the-range μP with a single FPGA. But there are many applications where a less-powerful μP can be quite helpful. Remember a μP trades performance of the hardwired solution with gate efficiency. In software, or when designed as an FSM, an algorithm like an FFT may ran slower, but usually needs much less resources. So the μP we build with FPGAs are more of the microcontroller type than a fully featured modern Intel Pentium or TI VLIW PDSP. A typical application we discuss later would be the implementation of a controller for a radix-2 FFT. Now you may argue that this can be done with an FSM. And yes that is true and we basically consider our FPGA μP design nothing else then an FSM augmented by a program memory that includes the operation the FSM will perform, see Fig. 9.1. In fact the early versions of the Xilinx PicoBlaze processor were called Ken Chapman programmable state machine (KCPSM) [284]. A complete μP design usually involves several steps, such as the architecture exploration phase, the instruction set design, and the development tools. We will discuss these steps in the following in more details. You are encouraged to study in addition a computer architecture book; there are many available today as this is a standard topic in most undergraduate computer engineering curricula [285, 286, 287, 288, 289, 290, 291].