Abstract
In this paper, we present a modification of XILINX’s Partial Reconfiguration Design Flow. Starting with either HDL-Design files or synthesised netlists, the presented flow generates all partial as well as the complete configuration bitstreams. In contrast to the established XILINX design flows, our flow is completely automated by a generator. By checking partial reconfiguration constraints it assists the user to avoid typical errors in module and bus macro placement. Compared with the PlanAhead partial reconfiguration flow, it is a single flow for generating multiple implementation for each reconfigurable area.
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© 2007 Springer Berlin Heidelberg
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Scholz, R. (2007). Adapting and Automating XILINX’s Partial Reconfiguration Flow for Multiple Module Implementations. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_12
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DOI: https://doi.org/10.1007/978-3-540-71431-6_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-71430-9
Online ISBN: 978-3-540-71431-6
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