Abstract
We have addressed in this paper the implementation of red-black multigrid smoothers on high-end microprocessors. Most of the previous work about this topic has been focused on cache memory issues due to its tremendous impact on performance. In this paper, we have extended these studies taking Simultaneous Multithreading (SMT) into account. With the introduction of SMT, new possibilities arise, which makes a revision of the different alternatives highly advisable. A new strategy is proposed that focuses on inter-thread sharing to tolerate the increasing penalties caused by memory accesses. Performance results on an IBM’s Power5 based system reveal that our alternative scheme can compete with and even improve sophisticated schemes based on tailored loop fusion and tiling transformations aimed at improving temporal locality.
This work has been supported by the Spanish research grants TIC 2002-750 and TIN 2005-5619.
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García, C., Prieto, M., Setoain, J., Tirado, F. (2007). Enhancing the Performance of Multigrid Smoothers in Simultaneous Multithreading Architectures. In: Daydé, M., Palma, J.M.L.M., Coutinho, Á.L.G.A., Pacitti, E., Lopes, J.C. (eds) High Performance Computing for Computational Science - VECPAR 2006. VECPAR 2006. Lecture Notes in Computer Science, vol 4395. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71351-7_34
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DOI: https://doi.org/10.1007/978-3-540-71351-7_34
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