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BURS-Based Instruction Set Selection

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Perspectives of Systems Informatics (PSI 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4378))

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Abstract

Application-specific processors (ASIPs) look very promising as a platform for embedded systems since they comprise both the flexibility of a programmable device and the efficiency of application-specific hardware. A number of approaches to design an application-specific instruction sets were introduced during the last years. We apply the BURS (Bottom-Up Rewrite System) technique which is commonly used for retargetable code generation to this problem. As a result a simple algorithm is presented that generates both instruction set and assembly code from the source program; this algorithm can be used for retargetable code generation as well.

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References

  1. Aho, A.V., Ganapathi, M., Tjiang, S.W.: Code generation using tree matching and dynamic programming. ACM Transactions on Programming Languages and Systems 11(4), 491–516 (1989)

    Article  Google Scholar 

  2. Aho, A.V., Johnson, S.C.: Optimal code generation for expression trees. Journal of the ACM 23(3), 488–501 (1979)

    Article  MathSciNet  Google Scholar 

  3. Brisk, P., et al.: Instruction generation and regularity extraction for reconfigurable processors. In: Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 262–269 (2002)

    Google Scholar 

  4. Clark, N., Zhong, H., Mahlke, S.: Processor acceleration through automated instruction set customization. In: Proc. 36th International Symposium on Microarchitectures (2003)

    Google Scholar 

  5. Comon, H., et al.: Tree Automata Techniques and Applications (2002), http://www.grappa.univ-lille3.fr/tata/

  6. Cong, J., et al.: Application-specific instruction generation for configurable processor architecture. In: Proc. of the 12th International Symposium on Field Programmable Gate Arrays, pp. 183–189 (2004)

    Google Scholar 

  7. Fraser, C.W., Hanson, D.R.: A retargetable compiler for ANSI C. ACM SIGPLAN Notices 26(10), 29–43 (1991)

    Article  Google Scholar 

  8. Fraser, C.W., Hanson, D.R.: A Retargetable C Compiler: Design and Implementation, p. 564. Addison-Wesley, Reading (1995)

    MATH  Google Scholar 

  9. Fraser, C.W., Hanson, D.R., Proebsting, T.A.: Engineering a simple, efficient code generator generator. ACM Letters on Programming Languages and Systems 1(3), 213–226 (1992)

    Article  Google Scholar 

  10. Fraser, C.W., Henry, R.R., Proebsting, T.A.: BURG — fast optimal instruction selection and tree parsing. SIGPLAN Notices 27(4), 68–76 (1992)

    Article  Google Scholar 

  11. Hanson, D.R.: Early experience with ASDL in lcc. Software – Practice & Experience 29(5), 417–435 (1999)

    Article  MathSciNet  Google Scholar 

  12. Hoffmann, C.M.: Pattern matching in trees. Journal of the ACM 29(1), 68–95 (1983)

    Article  Google Scholar 

  13. Huang, I.J., Despain, A.M.: Generating instruction sets and microarchitectures from applications. In: Proc. of the IEEE/ACM International Conference on Computer-Aided Design, pp. 391–396 (1994)

    Google Scholar 

  14. Huang, I.J., Despain, A.M.: Synthesis of instruction sets for pipelined microprocessors. In: Proc. of the 31th ACM/IEEE Design Automation Conference, pp. 5–11 (1994)

    Google Scholar 

  15. Kastner, R., et al.: Instruction generation for hybrid reconfigurable systems. ACM Trans. on Design Automation of Electronic Systems 7(4), 605–627 (2002)

    Article  Google Scholar 

  16. Praet, J.V., et al.: Instruction set definition and instruction selection for ASIPs. In: Proc. of the 7th ACM/IEEE International Symposium on High-Level Synthesis, pp. 11–16 (1994)

    Google Scholar 

  17. Zivojnovic, V., et al.: DSPstone: A DSP-oriented benchmarking methodology. In: Proc. International Conference on Signal Processing Applications and Technology (1994)

    Google Scholar 

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Irina Virbitskaite Andrei Voronkov

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© 2007 Springer-Verlag Berlin Heidelberg

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Boulytchev, D. (2007). BURS-Based Instruction Set Selection. In: Virbitskaite, I., Voronkov, A. (eds) Perspectives of Systems Informatics. PSI 2006. Lecture Notes in Computer Science, vol 4378. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70881-0_37

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  • DOI: https://doi.org/10.1007/978-3-540-70881-0_37

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-70880-3

  • Online ISBN: 978-3-540-70881-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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