Abstract
In the last years, several algorithms to implement the fuzzification stage for Very Large Scale of Integration (VLSI) Integrated Circuits (IC) using a Hardware Description Language (HDL) have been developed. In this work it is presented a proposal based in the arithmetic calculation of the slopes in triangular and trapezoidal membership functions to obtain a fuzzified value. We used an arithmetic calculation algorithm to implement trapezoidal and triangular membership functions. This proposal is different to others that at present time are currently used. We discuss the advantages and disadvantages of this implementation. A methodology to test and validate this stage through the Xilinx System Generator is described.
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Maldonado, Y., Montiel, O., Sepúlveda, R., Castillo, O. (2008). Design and Simulation of the Fuzzification Stage through the Xilinx System Generator. In: Castillo, O., Melin, P., Kacprzyk, J., Pedrycz, W. (eds) Soft Computing for Hybrid Intelligent Systems. Studies in Computational Intelligence, vol 154. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70812-4_16
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DOI: https://doi.org/10.1007/978-3-540-70812-4_16
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