Advertisement

Signature-Based Calibration of Analytical System-Level Performance Models

  • Stanley Jaddoe
  • Andy D. Pimentel
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5114)

Abstract

The Sesame system-level simulation framework targets efficient design space exploration of embedded multimedia systems. Even despite Sesame’s efficiency, it would fail to explore large parts of the design space simply because system-level simulation is too slow for this. Therefore, Sesame uses analytical performance models to provide steering to the system-level simulation, guiding it toward promising system architectures and thus pruning the design space. In this paper, we present a mechanism to calibrate these analytical models with the aim to deliver trustworthy estimates. Moreover, we also present some initial evaluation results with respect to the accuracy of our calibration mechanism using a case study with a Motion-JPEG encoder.

Keywords

Design Space Architecture Model Design Space Exploration Architecture Component Event Trace 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Pimentel, A.D., Erbas, C., Polstra, S.: A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Trans. on Computers 55, 99–112 (2006)CrossRefGoogle Scholar
  2. 2.
    Erbas, C., Pimentel, A.D., Thompson, M., Polstra, S.: A framework for system-level modeling and simulation of embedded systems architectures. EURASIP Journal on Embedded Systems (2007) doi:10.1155/2007/82123Google Scholar
  3. 3.
    Erbas, C., Cerav-Erbas, S., Pimentel, A.D.: A multiobjective optimization model for exploring multiprocessor mappings of process networks. In: Proc. of the int. conference on Hardware/Software Codesign & System Synthesis (CODES+ISSS), pp. 182–187 (2003)Google Scholar
  4. 4.
    Erbas, C., Cerav-Erbas, S., Pimentel, A.D.: Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. IEEE Trans. on Evolutionary Computation 10, 358–374 (2006)CrossRefGoogle Scholar
  5. 5.
    Kahn, G.: The semantics of a simple language for parallel programming. Information Processing 74, 471–475 (1974)MathSciNetGoogle Scholar
  6. 6.
    Keutzer, K., Malik, S., Newton, A., Rabaey, J., Sangiovanni-Vincentelli, A.: System level design: Orthogonalization of concerns and platform-based design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 19 (2000)Google Scholar
  7. 7.
    Qin, W., Malik, S.: Flexible and formal modeling of microprocessors with application to retargetable simulation. In: Design, Automation and Test in Europe (DATE) Conference, pp. 556–561 (2003)Google Scholar
  8. 8.
    Bammi, J.R., Harcoun, E., Kruijtzer, W., Lavagno, L., Lazarescu, M.: Software performance estimation strategies in a system level design tool. In: International Conference on Hardware Software Codesign (CODES), pp. 82–87 (2000)Google Scholar
  9. 9.
    Beltrame, G., Brandolese, C., Fornaciari, W., Salice, F., Sciuto, D., Trianni, V.: An assembly-level execution-time model for pipelined architectures. In: Proc. of Int. Conference on Computer Aided Design (ICCAD), pp. 195–200 (2001)Google Scholar
  10. 10.
    Giusto, P., Martin, G., Harcourt, E.: Reliable estimation of execution time of embedded software. In: Proc. of the Design, Automation, and Test in Europe (DATE) Conference, pp. 580–588 (2001)Google Scholar
  11. 11.
    Snavely, A., Carrington, L., Wolter, N.: Modeling application performance by convolving machine signatures with application profiles. In: Proc. of the IEEE Workshop on Workload Characterization, pp. 149–156 (2001)Google Scholar
  12. 12.
    Eeckhout, L., Nussbaum, S., Smith, J., De Bosschere, K.: Statistical simulation: adding efficiency to the computer designer’s toolbox. IEEE Micro 23, 26–38 (2003)CrossRefGoogle Scholar
  13. 13.
    Joseph, P., Vaswani, K., Thazhuthaveetil, M.: Construction and Use of Linear Regression Models for Processor Performance Analysis. In: Proc. of the Int. Symposium on High-Performance Computer Architecture, pp. 99–108 (2006)Google Scholar
  14. 14.
    Srinivasan, R., Cook, J., Lubeck, O.: Performance Modeling Using Monte Carlo Simulation. IEEE Computer Architecture Letters 5 (2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Stanley Jaddoe
    • 1
  • Andy D. Pimentel
    • 1
  1. 1.Computer Systems Architecture group Informatics InstituteUniversity of AmsterdamThe Netherlands

Personalised recommendations