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Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor

  • Emre Özer
  • Ronald G. Dreslinski
  • Trevor Mudge
  • Stuart Biles
  • Krisztián Flautner
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5114)

Abstract

This paper focuses on the instruction fetch resources in a real-time SMT processor to provide an energy-efficient configuration for a soft real-time application running as a high priority thread as fast as possible while still offering decent progress in low priority or non-real-time thread(s). We propose a fetch mechanism, Fetch-around, where a high priority thread accesses the L1 ICache, and low priority threads directly access the L2. This allows both the high and low priority threads to simultaneously fetch instructions, while preventing the low priority threads from thrashing the high priority thread’s ICache data. Overall, we show an energy-performance metric that is 13% better than the next best policy when the high performance thread priority is 10x that of the low performance thread.

Keywords

Caches Embedded Processors Energy Efficiency Real-time SMT 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Emre Özer
    • 1
  • Ronald G. Dreslinski
    • 2
  • Trevor Mudge
    • 2
  • Stuart Biles
    • 1
  • Krisztián Flautner
    • 1
  1. 1.ARM Ltd.CambridgeUK
  2. 2.Department of Electrical Engineering and Computer ScienceUniversity of MichiganAnn ArborUS

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