Design Issues in Parallel Array Languages for Shared Memory

  • James Brodman
  • Basilio B. Fraguela
  • María J. Garzarán
  • David Padua
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5114)


The Hierarchically Tiled Array (HTA) is a data type that facilitates the definition and manipulation of arrays partitioned into tiles. The data type allows to exploit those tiles to attain both locality and parallelism. Parallel programs written with HTAs are based in data parallelism, and provide the programmer with a single-threaded view of the execution. In our experience, HTAs help to develop parallel codes in a much more productive way than other parallel programming approaches. While we have worked extensively with HTAs in distributed memory environments, only recently have we began to consider their adaption to shared memory environments such as those found in multicore systems. In this paper we review the design issues, opportunities and challenges that this migration raises.


parallel programming data parallelism tiling shared memory 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Barnes, G.H., Brown, R.M., Kato, M., Kuck, D., Slotnick, D., Stokes, R.: The ILLIAC IV Computer. IEEE Transactions on Computers 8(17), 746–757 (1968)CrossRefGoogle Scholar
  2. 2.
    McKellar, A.C., Coffman, J.E.G.: Organizing Matrices and Matrix Operations for Paged Memory Systems. Communications of the ACM 12(3), 153–165 (1969)zbMATHCrossRefGoogle Scholar
  3. 3.
    Wolf, M.E., Lam, M.S.: A Data Locality Optimizing Algorithm. In: Proc. of the Conf. on Programming Language Design and Implementation, pp. 30–44 (1991)Google Scholar
  4. 4.
    High Performance Fortran Forum. High Performance Fortran Specification Version 2.0 (January 1997)Google Scholar
  5. 5.
    Chamberlain, B., Choi, S.: The Case for High Level Parallel Programming in ZPL. IEEE Computational Science and Engineering 5(3), 76–86 (1998)CrossRefGoogle Scholar
  6. 6.
    Carlson, W., Draper, J., Culler, D., Yelick, K., Brooks, E., Warren, K.: Introduction to UPC and Language Specification. Technical Report CCS-TR-99-157, IDA Center for Computing Sciences (1999)Google Scholar
  7. 7.
    Numrich, R.W., Reid, J.: Co-array Fortran for Parallel Programming. SIGPLAN Fortran Forum 17(2), 1–31 (1998)CrossRefGoogle Scholar
  8. 8.
    Bikshandi, G., Guo, J., Hoeflinger, D., Almasi, G., Fraguela, B.B., Garzarán, M.J., Padua, D., von Praun, C.: Programming for Parallelism and Locality with Hierarchically Tiled Arrays. In: PPoPP 2006: Proc. of the ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, pp. 48–57 (March 2006)Google Scholar
  9. 9.
    Guo, J., Bikshandi, G., Fraguela, B.B., Garzarán, M.J., Padua, D.: Programming with Tiles. In: PPoPP 2008: Proc. of the ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, pp. 111–122 (February 2008)Google Scholar
  10. 10.
    NAS Parallel Benchmarks,
  11. 11.
    Reinders, J.: Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism, 1st edn. O’Reilly, Sebastopol (July 2007)Google Scholar
  12. 12.
    Butenhof, D.R.: Programming with POSIX Threads. Addison Wesley, Reading (1997)Google Scholar
  13. 13.
    Chandra, R., Dagum, L., Kohr, D., Maydan, D., McDonald, J., Menon, R.: Parallel programming in OpenMP. Morgan Kaufmann Publishers, San Francisco (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • James Brodman
    • 1
  • Basilio B. Fraguela
    • 2
  • María J. Garzarán
    • 1
  • David Padua
    • 1
  1. 1.Dept. of Computer ScienceUniversity of Illinois at Urbana-ChampaignUrbanaUSA
  2. 2.Dept. de Electrónica y SistemasUniversidade da CoruñaA CoruñaSpain

Personalised recommendations