Memory-Centric Hardware Synthesis from Dataflow Models

  • Scott Fischaber
  • John McAllister
  • Roger Woods
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5114)


Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.


dataflow template matching hardware synthesis 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Scott Fischaber
    • 1
  • John McAllister
    • 1
  • Roger Woods
    • 1
  1. 1.Programmable Systems Laboratory:Institute for Electronic, Communication and Information Technology (ECIT)Queen’s University BelfastBelfastUK

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