Abstract
This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE (Instruction Set Extension) techniques. A case study demonstrates the methodological approach for the JPEG algorithm.
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Muhammad, R., Apvrille, L., Pacalet, R. (2008). Evaluation of ASIPs Design with LISATek. In: Bereković, M., Dimopoulos, N., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2008. Lecture Notes in Computer Science, vol 5114. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70550-5_20
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DOI: https://doi.org/10.1007/978-3-540-70550-5_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-70549-9
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