Evaluation of ASIPs Design with LISATek

  • Rashid Muhammad
  • Ludovic Apvrille
  • Renaud Pacalet
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5114)


This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE (Instruction Set Extension) techniques. A case study demonstrates the methodological approach for the JPEG algorithm.


LISATek ASIPs JPEG Customized Instructions 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Rashid Muhammad
    • 1
  • Ludovic Apvrille
    • 1
  • Renaud Pacalet
    • 1
  1. 1.System-on-Chip laboratoryLabSoC, GET/ENSTSophia-AntipolisFrance

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