Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors

  • Xu Guo
  • Zhimin Chen
  • Patrick Schaumont
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5114)


Hardware implementations of block ciphers have been intensively evaluated for years. The hardware profile, including the performance, area and power of a block cipher, only considers the block cipher as a standalone component, and does not consider it as a coprocessor in a system design. In this paper we consider system integration of AES and PRESENT crypto coprocessors, and analyze the system profile in a co-simulation environment and then on an actual FPGA-based SoC platform. Energy, performance and implementation results for both the AES- and PRESENT-based systems are presented. Our research emphasizes the need to consider energy efficiency and performance at system-level when evaluating a block cipher for real embedded systems. Simulation results reveal that the hardware/software interfaces, as the communication bottleneck, have major impact on the system performance. Experimental results further demonstrate that the PRESENT, a power-efficient light-weight block cipher with lower security level, becomes less energy-efficient than AES when system-integration overhead is included.


Smart Card Clock Cycle Block Cipher Advance Encryption Standard FPGA Implementation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Xu Guo
    • 1
  • Zhimin Chen
    • 1
  • Patrick Schaumont
    • 1
  1. 1.Virginia TechBlacksburgUSA

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