Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors
Hardware implementations of block ciphers have been intensively evaluated for years. The hardware profile, including the performance, area and power of a block cipher, only considers the block cipher as a standalone component, and does not consider it as a coprocessor in a system design. In this paper we consider system integration of AES and PRESENT crypto coprocessors, and analyze the system profile in a co-simulation environment and then on an actual FPGA-based SoC platform. Energy, performance and implementation results for both the AES- and PRESENT-based systems are presented. Our research emphasizes the need to consider energy efficiency and performance at system-level when evaluating a block cipher for real embedded systems. Simulation results reveal that the hardware/software interfaces, as the communication bottleneck, have major impact on the system performance. Experimental results further demonstrate that the PRESENT, a power-efficient light-weight block cipher with lower security level, becomes less energy-efficient than AES when system-integration overhead is included.
KeywordsSmart Card Clock Cycle Block Cipher Advance Encryption Standard FPGA Implementation
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