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A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs

  • Francesca Palumbo
  • Simone Secchi
  • Danilo Pani
  • Luigi Raffo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5114)

Abstract

Multi-Processor Systems-on-Chip (MPSoCs) are the most recent challenge of the VLSI technologies and Networks on Chip represent a high performance alternative to the traditional bus architectures. In this paper, a novel approach to the design of a dual-mode router, based on the idea of supporting both circuit and packet switching in a non-exclusive way, is presented and evaluated. This feature makes the proposed architecture suitable for MPSoCs which have to deal with heterogeneous traffic characteristics especially in terms of data size, such as the Massively Parallel Processors. Non-exclusivity enables packets latency reduction, which in turn implies lower task completion times, and also it increases throughput.

Keywords

Networks on Chip Dual-mode switching Non-exclusive switching Circuit switching 

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References

  1. 1.
    Jerraya, A.A., Wolf, W.: The what, why and how of MPSoC. The Morgan Kaufmann Series in Systems on Silicon, pp. 1–18 (2005)Google Scholar
  2. 2.
    Sohi, G.S., Breach, S.E., Vijaykumar, T.: Multiscalar processors. In: Proc. 22nd Annu. Int. Symp. Computer Architecture, pp. 414–425 (June 1995)Google Scholar
  3. 3.
    Benini, L., Micheli, G.D.: Networks on Chips: A New Paradigm for Component-Based MPSoC Design. The Morgan Kaufmann Series in Systems on Silicon, pp. 49–80 (2005)Google Scholar
  4. 4.
    Dally, W., Towles, B.: Principles and Practices of Interconnection Network. Morgan Kaufmann, San Francisco (2004)Google Scholar
  5. 5.
    Shin, K.G., Daniel, S.: Analysis and implementation of hybrid switching. IEEE Transaction on Computers, 211–219 (1996)Google Scholar
  6. 6.
    Rijpkema, E., Goossens, K., Radulescu, A., Dielissen, J., Meerbergen, J.V., Wielage, P., Waterlander, E.: Trade-offs in the design of a router with both guaranteed and best-effort services for network on chip. In: Proc. of the conference on Design, Automation and Test in Europe, vol. 1, pp. 294–302 (2003)Google Scholar
  7. 7.
    Goossens, K., Meerbergen, J.V., Peeters, A., Wielage, P.: Network on silicon: Combining best-effort and guaranteed services. In: Proc. of the Design, Automation and Test in Europe Conference and Exhibition, DATE (2002)Google Scholar
  8. 8.
    Hsu, S.H., Lin, Y.X., Jou, J.M.: Design of a dual-mode NoC router integrated with network interface for AMBA-based IPs. In: Proc. IEEE Asian Solid-State Circuits Conference, pp. 211–214 (2006)Google Scholar
  9. 9.
    Ahamad, B., Erdogan, A.T., Khawarm, S.: Architecture of a dynamically reconfigurable NoC for adaptive reconfigurable MPSoC. In: Proceedings of the first NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006) (2006)Google Scholar
  10. 10.
    Radulescu, A., Goossens, K.: Communication services for networks on silicon. Domain-Specific Processors: Systems, Architectures, Modelling, and Simulation 275–299 (2004)Google Scholar
  11. 11.
    Lahiri, K., Raghunathan, A., Dey, S.: Evaluation of the traffic-performance characteristics of system-on-chip communication architectures. In: Proc. of the 14th International Conference on VLSI Design, pp. 29–35 (2000)Google Scholar
  12. 12.
    Lo, V., Windisch, K., Liu, W., Nitzberg, B.: Noncontiguous processor allocation algorithms for mesh-connectedmulticomputers. IEEE Transactions on Parallel and Distributed Systems 8(7), 712–726 (1997)CrossRefGoogle Scholar
  13. 13.
    Wu, F., Hsu, C., Chou, L.: Processor allocation in the mesh multiprocessors using the leapfrog method. IEEE Transactions on Parallel and Distributed Systems, 273–289 (2003)Google Scholar
  14. 14.
    Palumbo, F., Pani, D., Raffo, L., Secchi, S.: A surface tension and coalescence model for dynamic distributed resources allocation in massively parallel processors on-chip. In: Proc. International Workshop on Nature Inspired Cooperative Strategies for Optimization - NICSO 2007, Acireale, Italy (November 2007)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Francesca Palumbo
    • 1
  • Simone Secchi
    • 1
  • Danilo Pani
    • 1
  • Luigi Raffo
    • 1
  1. 1.DIEE - Dept. of Electrical and Electronic EngineeringUniversity of CagliariCagliariItaly

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