Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields
Finite field multiplication is one of the most important operations in the finite field arithmetic. Recently, a variation of the polynomial basis, which is known as the shifted polynomial basis, has been introduced. Current research shows that this new basis provides better performance in designing bit-parallel and subquadratic space complexity multipliers over binary extension fields. In this paper, we study digit-serial multiplication algorithms using the shifted polynomial basis. They include a Most Significant Digit (MSD)-first digit-serial multiplication algorithm and a hybrid digit-serial multiplication algorithm, which includes parallel computations. Then, we explain the hardware architectures of the proposed algorithms and compare them to their existing counterparts. We show that our MSD-first digit-serial shifted polynomial basis multiplier has the same complexity of the Least Significant Digit (LSD)-first polynomial basis multiplier. Also, we present the results for the hybrid digit-serial multiplier which offers almost the half of the latency of the best known digit-serial polynomial basis multipliers.
KeywordsShifted polynomial basis multiplication binary extension fields digit-serial
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