Abstract
Pipeline scaling provides an attractive solution for increasingly serious branch misprediction penalties within deep pipeline processor. In this paper we investigate Adaptive Pipeline Scaling (APS) techniques that are related to reducing branch misprediction penalties. We present a dual supply-voltage architecture framework that can be efficiently exploited in an deep pipeline processor to reduce pipeline depth depending on the confidence level of branches in pipeline. We also propose two techniques, Dual Path Index Table (DPIT) and Step-By-Step (STEP) manner, that increase the efficiency for pipeline scaling . With these techniques, we then show that APS not only provides a fast branch misprediction recovery, but also speeds up the resolve of mispredicted branch. The evaluation of APS in a 13-stage superscalar processor with benchmarks from SPEC2000 applications shows a performance improvement (between 3%-12%, average 8%) over baseline processor that does not exploit APS.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer Berlin Heidelberg
About this paper
Cite this paper
Yeh, CC., Chang, KC., Chen, TF., Yeh, C. (2007). Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. In: De Bosschere, K., Kaeli, D., Stenström, P., Whalley, D., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2007. Lecture Notes in Computer Science, vol 4367. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-69338-3_8
Download citation
DOI: https://doi.org/10.1007/978-3-540-69338-3_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-69337-6
Online ISBN: 978-3-540-69338-3
eBook Packages: Computer ScienceComputer Science (R0)