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References
R. E. Best, Phase-locked Loops, Theory, Design and Applications, McGraw Hill, 1993.
G. von Büren, C. Kromer, F. Ellinger, A. Huber, M. Schmatz and H. Jäckel, “A combined dynamic and static frequency divider for a 40 GHz PLL in 80 nm CMOS“, IEEE International Solid-State Circuits Conference, pp. 598–599, Feb. 2006.
B. de Muer, CMOS Fractional-N Synthesizers, Kluwer, 2003.
H. R. Rategh, T. H. Lee, Multi-GHz Frequency Synthesis & Division, Kluwer Academic, 2001.
B. Razavi, Monolithic Phase-locked Loops and Clock Recovery Circuits – a tutorial, Wiley, April 1996.
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© 2008 Springer-Verlag Berlin Heidelberg
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Ellinger, F. (2008). Phase Locked Loops and Synthesisers. In: Ellinger, F. (eds) Radio Frequency Integrated Circuits and Technologies. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-69325-3_12
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DOI: https://doi.org/10.1007/978-3-540-69325-3_12
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