ASIC Hardware Performance
This chapter presents detailed hardware implementation results and performance metrics for the eSTREAM candidate stream ciphers remaining in the Phase 3 hardware profile. Performance assessment has been made in accordance with the eSTREAM hardware testing framework in terms of power, area and speed. An attempt has been made to quantify the flexibility and scalability dimensions of performance. The results are presented in tabular and graphical format together with summarising the utility of the candidates against two notional applications: one for 10Mbps wireless network and a second for 100kHz RFID. Where applicable to a particular cipher, guidance on any limitations on the choice of key or IV is given. The chapter concludes with a summary of the performance of each of the candidates and some general guidance for future low resource hardware stream cipher development.
KeywordsShift Register Advance Encryption Standard Initialisation Vector Stream Cipher Linear Feedback Shift Register
Unable to display preview. Download preview PDF.
- 1.ECRYPT, Call for Stream Cipher Primitives (April 12, 2005), http://www.ecrypt.eu.org/stream/call/
- 2.Batina, L., Kumar, S., Lano, J., Lemke, K., Mentens, N., Paar, C., Preneel, B., Sakiyama, K., Verbauwhede, I.: Testing Framework for eSTREAM Profile II Candidates. In: SASC (2006), www.ecrypt.eu.org/stream
- 3.Good, T., Chelton, W., Benaissa, M.: Review of stream cipher candidates from a low resource hardware perspective. In: SASC (2006), www.ecrypt.eu.org/stream
- 4.Good, T., Benaissa, M.: Hardware results for selected stream cipher candidates. In: SASC (2007), www.ecrypt.eu.org/stream
- 5.Good, T., Benaissa, M.: Hardware performance of phase-III stream cipher candidates. In: SASC (2008), www.ecrypt.eu.org/stream
- 6.Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A Compact Rijndael Hardware Architecture with S-Box Optimization. In: Nagi, K. (ed.) Transactional Agents. LNCS, vol. 2249, pp. 230–254. Springer, Heidelberg (2001)Google Scholar