Advertisement

Code Optimization by Integer Linear Programming

  • Daniel Kästner
  • Marc Langenbach
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1575)

Abstract

The code quality of many high-level language compilers in the field of digital signal processing is not satisfactory. This is mostly due to the complexity of the code generation problem together with the irregularity of typical DSP architectures. Since digital signal processors mostly are traded on the high volume consumer market, they are subject to serious cost constraints. On the other hand, many embedded applications demand high performance capacities. Thus, it is very important that the features of the processor are exploited as efficiently as possible. By using integer linear programming (ILP), the deficiencies of the decoupling of different code generation phases can be removed, since it is possible to integrate instruction scheduling and register assignment in one homogeneous problem description. This way, optimal solutions can be found-albeit at the cost of high compilation times. Our experiments show, that approximations based on integer linear programming can provide a better solution quality than classical code generation algorithms in acceptable runtime for medium sized code sequences. The experiments were performed for a modern DSP, the Analog Devices ADSP-2106x.

Keywords

Integer Linear Programming Digital Signal Processor Resource Type Code Optimization Very Large Scale Integration 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Analog Devices. ADSP-2106x SHARC User’s Manual (1995)Google Scholar
  2. 2.
    Arya, S.: An Optimal Instruction Scheduling Model for a Class of Vector Processors. IEEE Transactions on Computers C-34 (November 1985)Google Scholar
  3. 3.
    Bieker, U., Bashford, S.: Scheduling, Compaction and Binding in a Retargetable Code Generator Using Constraint Logic Programming. In: 4. GI/ITG/GME Workshop ”Methoden des Entwurfs und der Verifikation digitaler Systeme”, Kreischa, Germany (March 1996)Google Scholar
  4. 4.
    Bradlee, D.G.: Retargetable Instruction Scheduling for Pipelined Processors. Phd thesis, Technical Report 91-08-07, University of Washington (1991)Google Scholar
  5. 5.
    Briggs, P., Cooper, K., Torczon, L.: Improvements to Graph Coloring Register Allocation. ACM Transactions on Programming Languages and Systems 16(3), 428–455 (1994)CrossRefGoogle Scholar
  6. 6.
    Callahan, D., Koblenz, B.: Register Allocation via Hierarchical Graph Coloring. In: Proceedings of the ACM PLDI Conference, pp. 192–202 (1991)Google Scholar
  7. 7.
    Chaudhuri, S., Walker, R.A., Mitchell, J.E.: Analyzing and Exploiting the Structure of the Constraints in the ILP-Approach to the Scheduling Problem. IEEE Transactions on Very Large Scale Integration (VLSI) System 2(4), 456–471 (1994)CrossRefGoogle Scholar
  8. 8.
    Fisher, J.A.: Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers C-30(7), 478–490 (1981)Google Scholar
  9. 9.
    Gebotys, C.H., Elmasry, M.I.: Optimal VLSI Architectural Synthesis. Kluwer Academic, Dordrecht (1992)Google Scholar
  10. 10.
    Gebotys, C.H., Elmasry, M.I.: Global Optimization Aproach for Architectural Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD-12(9), 1266–1278 (1993)Google Scholar
  11. 11.
    Govindarajan, R., Altman, E.R., Gao, G.R.: A Framework for Resource Constrained Rate Optimal Software Pipelining. IEEE Transactions on Parallel and Distributed Systems 7(11) (November 1996)Google Scholar
  12. 12.
    Gupta, R., Soffa, M.L.: Region scheduling: An approach for detecting and redistributing parallelism. IEEE Transactions on Software Engineering 16(4), 421–431 (1990)CrossRefGoogle Scholar
  13. 13.
    Hanono, S., Devadas, S.: Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In: Proceedings of the DAC 1998, San Francisco, California. ACM, New York (1998)Google Scholar
  14. 14.
    Kästner, D.: Instruktionsanordnung und Registerallokation auf der Basis ganzzahliger linearer Programmierung für den digitalen Signalprozessor ADSP-2106x. Master’s thesis, University of the Saarland (1997)Google Scholar
  15. 15.
    Kästner, D., Langenbach, M.: Integer Linear Programming vs. Graph Based Methods in Code Generation. Technical Report A/01/98, University of the Saarland, Saarbrücken, Germany (January 1998)Google Scholar
  16. 16.
    Landskov, D., Davidson, S., Shriver, B., Mallet, P.W.: Local Microcode Compaction Techniques. ACM Computing Surveys 12(3), 261–294 (1980)CrossRefGoogle Scholar
  17. 17.
    Langenbach, M.: Instruktionsanordnung unter Verwendung graphbasierter Algorithmen für den digitalen Signalprozessor ADSP-2106x. Master’s thesis, University of the Saarland (1997)Google Scholar
  18. 18.
    Leupers, R.: Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, Dordrecht (1997)zbMATHGoogle Scholar
  19. 19.
    Nemhauser, G.L., Rinnooy Kan, A.H.G., Todd, M.J. (eds.): Handbooks in Operations Research and Management Science, vol. 1. North-Holland, Amsterdam (1989)Google Scholar
  20. 20.
    Nemhauser, G.L., Wolsey, L.A.: Integer and Combinatorial Optimization. John Wiley and Sons, New York (1988)Google Scholar
  21. 21.
    Nicolau, A.: Uniform parallelism exploitation in ordinary programs. In: International Conference on Parallel Processing, pp. 614–618. IEEE Computer Society Press, Los Alamitos (1985)Google Scholar
  22. 22.
    Papadimitriou, C.H., Steiglitz, K.: Combinatorial Optimization, Algorithms and Complexity. Prentice-Hall, Englewood Cliffs (1982)Google Scholar
  23. 23.
    Papadimitriou, C.H., Steiglitz, K.: Combinatorial Optimization, Algorithms and Complexity, ch-13, pp. 318–322. Prentice-Hall, Englewood Cliffs (1982)Google Scholar
  24. 24.
    Ruttenberg, J., Gao, G.R., Stoutchinin, A., Lichtenstein, W.: Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler. In: Proceedings of the 1996 ACM SIGPLAN Conference on Programming Languages Design and Implementation (PLDI 1996), vol. 31(5), May 1996, pp. 1–11 (1996)Google Scholar
  25. 25.
    Saghir, M.A.R., Chow, P., Lee, C.G.: Exploiting Dual Data-Memory Banks in Digital Signal Processors (1996), http://www.eecg.toronto.edu/~saghir/papers/asplos7.ps
  26. 26.
    SPAM Research Group, http://www.ee.princeton.edu/spam SPAM Compiler User’s Manual (September 1997)
  27. 27.
    Sudarsanam, A.: Code Optimization Libraries for Retargetable Compilation for Embedded Digital Signal Processors. PhD thesis, University of Princeton (November 1998)Google Scholar
  28. 28.
    Wilson, T., Grewal, G., Henshall, S., Banerji, D.: An ILP-Based Approach to Code Generation. In: Marwedel, P., Goossens, G. (eds.) Code Generation for Embedded Processors, ch. 6, pp. 103–118. Kluwer, Dordrecht (1995)Google Scholar
  29. 29.
    Zhang, L.: SILP. Scheduling and Allocating with Integer Linear Programming. PhD thesis, University of the Saarland, Technical Faculty (1996)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Daniel Kästner
    • 1
  • Marc Langenbach
    • 1
  1. 1.Fachbereich InformatikUniversität des SaarlandesSaarbrückenGermany

Personalised recommendations