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Extending Modulo Scheduling with Memory Reference Merging

  • Benoît Dupont de Dinechin
Conference paper
  • 418 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1575)

Abstract

We describe an extension of modulo scheduling, called “memory reference merging”, which improves the management of cache bandwidth on microprocessors such as the DEC Alpha 21164. The principle is to schedule together memory references that are likely to be merged in a read buffer (LOADs), or a write buffer (STOREs). This technique has been used over several years on the Cray T3E block scheduler, and was later generalized to the Cray T3E software pipeliner. Experiments on the Cray T3E demonstrate the benefits of memory reference merging.

Keywords

Memory Reference Memory Hierarchy Loop Body Software Pipeline Cache Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Benoît Dupont de Dinechin
    • 1
  1. 1.CMG/MDT DivisionST Microelectronics 

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