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FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding

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Field Programmable Logic and Applications (FPL 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1673))

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Abstract

Reed-Solomon codes are widely used in communications as well as in data storage for the correction of errors due to channel noise. In this paper we present a comparison between implementations of the Berlekamp-Massey algorithm and the Fitzpatrick algorithm. Both algorithms were synthesised and implemented on an FPGA and compared in terms of area, speed and routability. The modules can be used as part of a core-based design for Reed-Solomon decoders.

The research presented in this paper has been supported by Silicon Systems Limited and Forbairt under Applied Research Scheme Grant HE/97/302

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© 1999 Springer-Verlag Berlin Heidelberg

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Popovici, E.M., Fitzpatrick, P., Murphy, C.C. (1999). FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_37

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  • DOI: https://doi.org/10.1007/978-3-540-48302-1_37

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-66457-4

  • Online ISBN: 978-3-540-48302-1

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