PulseDSP – A Signal Processing Oriented Programmable Architecture

Abstract

Classical digital signal conditioning algorithms, such as FIR filtering, involve many simple independent calculations repeated in a fixed order. This makes them particularly appropriate for implementation using a parallel processing approach. The PulseDSP architecture is a programmable array developed to exploit this inherent parallelism. The architecture is a systolic array of simple processing elements. Data is passed between processing elements using a programmable network of serial data channels. Each processing element performs basic fixed operations on the data before passing it the next element. Algorithms are implemented by structurally describing the calculation as a signal flow then mapping it to the array on a one-to-one, operation-to-processor basis. This approach can provide a significant improvement in performance over standard DSP processor and FPGA implementations, particularly when large datawidths are required.