Abstract
A digital hardware implementation of an algorithm modelling the “effective” signal processing of the human auditory system is presented in this paper. The model can be used as a preprocessor for speech, for example in automatic speech recognition, objective speech quality measurement, noise reduction and digital hearing aids.
A direct hardware implementation of the floating point software version of the model has many disadvantages. The main problem when converting floating point arithmetic to fixed point arithmetic is the determination of the necessary numerical precision which implies the wordlength of internal number representation. The necessary internal wordlength for the linear parts of the system can be assessed in a straight-forward way because the filters are linear time invariant systems, where classical numerical parameters like SNR can be applied. For the realization of the nonlinear parts this procedure is not applicable. One application of the model(objective speech quality measurement) was used to determine the necessary internal precision. By observing the degradiation of the performance with decreasing internal precision it shows that necessary internal wordlength can be reduced while the performance almost stays the same. To validate the approach a prototype of the design was implemented on a Xilinx XC40200XV-09.
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References
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Brucke, M., Schulz, A., Nebel, W. (1999). Auditory Signal Processing in Hardware. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_2
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DOI: https://doi.org/10.1007/978-3-540-48302-1_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
Online ISBN: 978-3-540-48302-1
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