Skip to main content
SpringerLink
Log in
Book cover

International Workshop on Field Programmable Logic and Applications

FPL 1999: Field Programmable Logic and Applications pp 124–133Cite as

DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems

  • Conference paper

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1673))

Abstract

This paper presents DYNASTY–a new CAD framework aimed at supporting research of design techniques, algorithms and methodologies for dynamically reconfigurable logic (DRL) systems. Design flow implemented in the DYNASTY Framework is based around a temporal floorplanning (TF) DRL design abstraction, which allows simultaneous DRL design space exploration in spatial and temporal dimensions.

The paper introduces temporal floorplanning and its implementation in the DYNASTY Framework. Methodologies based on temporal floorplanning promise reduction of design time and elimination of costly design iterations present in traditional DRL design methodologies.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Vasilko, M., Gibson, D., Long, D., Holloway, S.: Towards a consistent design methodology for run-time reconfigurable systems. In: IEE Colloquium on Reconfigurable Systems, Digest No.99/061, Glasgow, Scotland, March 10, pp. 5/1–4 (1999)

    Google Scholar 

  2. Lysaght, P.: Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic. In: Luk et al. [14], pp. 183–192.

    Google Scholar 

  3. Kaul, M., Vemuri, R.: Optimal temporal partitioning and synthesis for reconfigurable architectures. In: Design, Automation and Test in Europe Conference, Paris, France, February 23-26 (1998)

    Google Scholar 

  4. Vasilko, M., Ait-Boudaoud, D.: Architectural synthesis techniques for dynamically reconfigurable logic. In: Glesner, M., Hartenstein, R.W. (eds.) FPL 1996. LNCS, vol. 1142, pp. 290–296. Springer, Heidelberg (1996)

    Google Scholar 

  5. Bazargan, K., Kaster, R., Sarrafzadeh, M.: 3-D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems. In: Proc. IEEE Workshop on Rapid System Prototyping (RSP 1999), Clearwater, FL, USA, June 16-18 (1999)

    Google Scholar 

  6. Xilinx, XC6200 Field Programmable Gate Arrays, Advanced Product Information Xilinx, Inc. Version 1.10 (April 1997)

    Google Scholar 

  7. Lysaght, P., Stockwood, J.: A simulation tool for dynamically reconfigurable field programmable gate arrays. IEEE Transactions on VLSI Systems 4(3), 381–390 (1996)

    Article  Google Scholar 

  8. Vasilko, M., Cabanis, D.: Improving simulation accuracy in design methodologies for dynamically reconfigurable logic systems. In: Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 1999), Napa, CA, USA, April 21-23 (1999)

    Google Scholar 

  9. Stanford, P., Mancuso, P. (eds.): EDIF Electronic Design Interchange Format Version 2. 0 0. Electronic Industries Association, 2nd ed. (1990)

    Google Scholar 

  10. Betz, V., Rose, J.: VPR: A new packing, placement and routing tool for FPGA research. In: Luk et al. [14], pp. 213–222.

    Google Scholar 

  11. Foulk, P., Hodson, I.: Data folding in SRAM configurable FPGAs. In: Buell, D.A., Pocek, K.L. (eds.) Proc. IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, USA, April 5-7 (1993)

    Google Scholar 

  12. Dewilde, P., Deprettere, E., Nouta, R.: Parallel and pipelined VLSI implementation of signal processing algorithms. In: Kung, S., Whitehouse, H., Kailath, T. (eds.) VLSI and Modern Signal Processing, pp. 257–264. Prentice Hall, Englewood Cliffs (1985)

    Google Scholar 

  13. Paulin, P.G., Knight, J.P.: Algorithms for high-level synthesis. IEEE Design and Test of Computers 6(3), 18–31 (1989)

    Google Scholar 

  14. Luk, W., Cheung, P.Y.K., Glesner, M.: Field Programmable Logic and Applications (Proc. FPL 1997). In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS. vol. 1304. Springer, Heidelberg (1997)

    Chapter  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Microelectronic Systems Research Group, School of DEC, Bournemouth University, Talbot Campus, Fern Barrow, Poole, Dorset, BH12 5BB, UK

    Milan Vasilko

Authors
  1. Milan Vasilko
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Xilinx Research Labs, 2100 Logic Drive, CA 95032, San Jose, California

    Patrick Lysaght

  2. Department of Electrical and Electronic Engineering, University of Strathclyde, 204 George St., G1 1XW, Glasgow, UK

    James Irvine

  3. Technical University of Kaiserslautern, Germany

    Reiner Hartenstein

Rights and permissions

Reprints and permissions

Copyright information

© 1999 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Vasilko, M. (1999). DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_13

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-48302-1_13

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-66457-4

  • Online ISBN: 978-3-540-48302-1

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation