Abstract
On-chip storage has become critical in large FPGAs. This has led most FPGA vendors to include configurable embedded arrays in their devices. Because of the large number of ways in which the arrays can be combined, and because of the configurability of each array, there are often many ways to implement the memories required by a circuit. Implementing user memories using physical arrays is called logical-to-physical mapping, and has previously been studied for single-port FPGA memory arrays. Most current FPGAs, however, contain dual-port arrays. In this paper, we present a logical-to-physical algorithm that specifically targets dual-port FPGA arrays. We show that this algorithm results in 28% denser memory implementations than the only previously published algorithm.
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References
Altera Corporation. Datasheet: FLEX 10K Embedded Programmable Logic Family (May 1998)
Altera Corporation. Datasheet: FLEX 10KE Embedded Programmable Logic Family (August 1998)
Xilinx, Inc., Virtex: Our new million-gate 100-MHz FPGA technology. XCell: The Quarterly Journal for Xilinx Programmable Logic Users, First Quarter (1998)
Actel Corporation. Datasheet: Integrator Series FPGAs: 40MX and 42MX Families (April 1998)
Lattice Semiconductor Corporation. Datasheet: ispLSI and pLSI 6192 High Density Programmable Logic with Dedicated Memory and Register/Counter Modules (July 1996)
Wilton, S.J.E.: Architectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memory. PhD thesis, University of Toronto (1997)
Wilton, S.J.E.: SMAP: heterogeneous technology mapping for FPGAs with embedded memory arrays. In: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 1998, pp. 171–178 (1998)
Cong, J., Xu, S.: Technology mapping for FPGAs with embedded memory blocks. In: Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 1998, pp. 179–187 (1998)
Altera Corporation, Implementing RAM functions in FLEX 10K devices. Technical Note (November 1995)
Jha, P.K., Dutt, N.D.: Library mapping for memories. In: Proceedings of the 1997 European Design and Test Conference (March 1997)
Karchmer, D., Rose, J.: Definition and solution of the memory packing problem for field-programmable systems. In: Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 20–26 (1994)
Schmit, H., Thomas Jr., D.: Address generation for memories containing multiple arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17 (May 1998)
Panda, P.R., Dutt, N.D.: Behavioral array mapping into multiport memories targeting low power. In: Proceedings of the 10th International Conference on VLSI Design (January 1997)
Balakrishnan, M., Majumdar, A., Banerji, D., Linders, J., Majithia, J.: Allocation of multiport memories in datapath synthesis. IEEE Transactions on Computer-Aided Design 7 (April 1988)
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© 1999 Springer-Verlag Berlin Heidelberg
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Ho, W.K.C., Wilton, S.J.E. (1999). Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_12
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DOI: https://doi.org/10.1007/978-3-540-48302-1_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
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