Abstract
Current embedded multimedia applications have stringent time and power constraints. Coarse-grained reconfigurable processors have been shown to achieve the required performance. However, there is not much research regarding the power consumption of such processors. In this paper, we present a novel coarse-grained reconfigurable processor and study its power consumption using a power model derived from Wattch. Several processor configurations are evaluated using a set of multimedia applications. Results show that the presented coarse-grained processor can achieve on average 2.5x the performance of a RISC processor with an 18% increase in energy consumption.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Trimaran: An infrastructure for instruction level parallelism (1999), http://www.trimaran.org
Barat, F., Jayapala, M., Beeck, P.O.d., Deconinck, G.: Software pipelining for coarse-grained reconfigurable instruction set processors. In: Proc. ASP-DAC, January 2002, pp. 338–344 (2002)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: Proc. 27th Int’l Symp. Computer Architecture (ISCA 2000), June 2000, pp. 83–94 (2000)
Goldstein, S.C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R.R., Laufer, R.: PipeRench: a coprocessor for streaming multimedia acceleration. In: Proc. 26th Int’l Symp. Computer Architecture (ISCA 1999), May 1999, pp. 28–39 (1999)
Liao, W., He, L.: Power Modeling and Reduction of VLIW Processors. In: Compilers and Operating Systems for Low Power, Kluwer Academic Publishers, Dordrecht (2002)
Lu, G., Singh, H., Lee, M.-H., Bagherzadeh, N., Kurdahi, F.J., Filho, E.M.C.: The morphosys parallel reconfigurable system. In: European Conference on Parallel Processing, pp. 727–734 (1999)
Miyamori, T., Olukotun, K.: REMARC: Reconfigurable multimedia array coprocessor. In: Proc. 6th Int’l Symp. Field-Programmable Gate Arrays (FPGA 1998) (February 1998)
Poon, K.K.W., Yan, A., Wilton, S.J.E.: A flexible power model for fpgas. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, p. 312. Springer, Heidelberg (2002)
Ye, W., Vijaykrishnan, N., Kandemir, M.T., Irwin, M.J.: The design and use of simplepower: a cycle-accurate energy estimation tool. In: Proc. DAC, June 2000, pp. 340–345 (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Barat, F., Jayapala, M., Vander Aa, T., Lauwereins, R., Deconinck, G., Corporaal, H. (2003). Low Power Coarse-Grained Reconfigurable Instruction Set Processor. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_23
Download citation
DOI: https://doi.org/10.1007/978-3-540-45234-8_23
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
eBook Packages: Springer Book Archive