Abstract
The design of a routing channel for an FPGA is a complex process requiring a careful balance of flexibility with silicon efficiency. With a growing move towards embedding FPGAs into SoC designs, and the new opportunity to automatically generate FPGA architectures, this problem is even more critical. The design of a routing channel requires determining the number of routing tracks, the length of the wires in those tracks, and the positioning of the breaks between wires on the tracks. This paper focuses on the last problem, the placement of breaks in tracks to maximize overall flexibility. Our optimal algorithm for track placement finds a best solution provided the problem meets a number of restrictions. Our relaxed algorithm is without restrictions, and finds solutions on average within 1.13% of optimal.
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References
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Compton, K., Hauck, S.: Track Placement: Orchestrating Routing Structures to Maximize Routability, University of Washington Technical Report UWEETR-2002-0013 (2002)
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Compton, K., Hauck, S. (2003). Track Placement: Orchestrating Routing Structures to Maximize Routability. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_13
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DOI: https://doi.org/10.1007/978-3-540-45234-8_13
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