Energy-Conscious Memory Allocation and Deallocation for Pointer-Intensive Applications

  • Victor De La Luz
  • Mahmut Kandemir
  • Guangyu Chen
  • Ibrahim Kolcu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2855)


A multi-bank memory architecture is composed of multiple memory banks, each of which can be energy-managed independently. In this paper, we present a set of strategies for reducing energy consumption in a multi-bank memory architecture using energy-conscious dynamic memory allocation/deallocation. Applications that make dynamic memory allocations are used very frequently in mobile computing/networking area. Our strategies focus on such applications and try to cluster dynamically created data with temporal affinity in the physical address space such that the data occupy a small number of memory banks. The remaining banks can be shut off, saving energy. All of our strategies have been implemented and tested using an in-house energy simulator and an application suite that consists of nine pointer-intensive real-life applications. Our results show that all the strategies considered in this paper save energy (e.g., our user-initiated strategy saves 49% leakage energy on the average). The results also indicate that the best savings are obtained when energy-aware memory allocation/deallocation is combined with automatic data migration.


Memory Allocation Memory Bank Memory Controller Instruction Cache Page Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Catthoor, F., Wuytack, S., Greef, E.D., Balasa, F., Nachtergaele, L., Vandecappelle, A.: Custom Memory Management Methodology – Exploration of Memory Organization for Embedded Multimedia System Design. Kluwer Academic Publishers, Dordrecht (1998)Google Scholar
  2. 2.
    Chandrakasan, A., Bowhill, W.J., Fox, F.: Design of High-Performance Microprocessor Circuits. IEEE Press, Los Alamitos (2001)Google Scholar
  3. 3.
    Chen, G., Shetty, R., Kandemir, M., Vijaykrishnan, N., Irwin, M.J., Wolczko, M.: Tuning garbage collection in an embedded Java environment. In: Proc. the 8th International Symposium on High-Performance Computer Architecture, Cambridge, MA, February 2-6 (2002)Google Scholar
  4. 4.
    Chilimbi, T.M., Hill, M.D., Larus, J.R.: Cache-conscious structure layout. In: Proc. the ACM Conference on Programming Languages Design and Implementation (May 1999)Google Scholar
  5. 5.
    Cmelik, B., Keppel, D.: Shade: A Fast Instruction-Set Simulator for Execution Profiling. In: Proc. the ACM SIGMETRICS Conference on the Measurement and Modeling of Computer Systems, May 1994, pp. 128–137 (1994)Google Scholar
  6. 6.
    Delaluz, V., Kandemir, M., Vijaykrishnan, N., Sivasubramaniam, A., Irwin, M.J.: DRAM energy management using software and hardware directed power mode control. In: Proc. the 7th International Conference on High Performance Computer Architecture, Monterrey, Mexico (January 2001)Google Scholar
  7. 7.
    Ellervee, P., Miranda, M., Catthoor, F., Hemani, A.: System-level data format exploration for dynamically allocated data structures. In: Proc. the 37th ACM Design Automation Conference, Los Angeles, CA, June 2000, pp. 556–559 (2000)Google Scholar
  8. 8.
    Grunwald, D., Zorn, B.: CUSTOMALLOC: efficient synthesized memory allocators. Technical Report CU-CS-602-92, Department of Computer Science, University of Colorado, Boulder, CO (July 1992)Google Scholar
  9. 9.
    Grunwald, D., Zorn, B., Henderson, R.: Improving the cache locality of memory allocation. In: Proc. the ACMConference on Programming Languages and Implementation, June 1993, pp. 177–186 (1993)Google Scholar
  10. 10.
  11. 11.
    Hanson, D.R.: Fast allocation and deallocation of memory based on object lifetimes. Software Practice and Experience 20(1), 5–12 (1990)CrossRefMathSciNetGoogle Scholar
  12. 12.
    Hanson, H., Hrishikesh, M.S., Agarwal, V., Keckler, S.W., Burger, D.: Static energy reduction techniques for microprocessor caches. In: Proc. the 2001 International Conference on Computer Design (2001)Google Scholar
  13. 13.
    Hemani, A., Svantesson, B., Ellervee, P., Postula, A., Oberg, J., Jantsch, A., Tenhunen, H.: High-level synthesis of control and memory intensive communication systems. In: Proc. the 8th Annual IEEE International ASIC Conference and Exhibit, September 1995, pp. 185–191 (1995)Google Scholar
  14. 14.
    IBM Datasheet for Travelstar 48GH Disk (2000)Google Scholar
  15. 15.
    Kamble, M., Ghose, K.: Analytical energy dissipation models for low power caches. In: Proc. the International Symposium on Low Power Electronics and Design, August 1997, p. 143 (1997)Google Scholar
  16. 16.
    Kingsley, C.: Description of a very fast storage allocator. Documentation of 4.2 BSD Unix malloc implementation (February 1982)Google Scholar
  17. 17.
    Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: Proc. the 28th International Symposium on Computer Architecture, Sweden (June 2001)Google Scholar
  18. 18.
    Kim, N.S., Flautner, K., Blaauw, D., Mudge, T.: Drowsy instruction caches. In: Proc. the 35th International Symposium on Microachitecture, Istanbul, Turkey (2002)Google Scholar
  19. 19.
  20. 20.
    Lebeck, R., Fan, X., Zeng, H., Ellis, C.S.: Power aware page allocation. In: Proc. the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (November 2000)Google Scholar
  21. 21.
    Li, L., Kadayif, I., Tsai, Y.-F., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Sivasubramaniam, A.: Leakage energy management in cache hierarchies. In: Proc. the 11th International Conference on Parallel Architectures and Compilation Techniques, Charlottesville, Virginia (September 2002)Google Scholar
  22. 22.
    Powell, M.D., Yang, S., Falsafi, B., Roy, K., Vijaykumar, T.N.: Reducing Leakage in a High-Performance Deep-Submicron Instruction Cache. IEEE Transactions on VLSI 9(1) (February 2001)Google Scholar
  23. 23.
    Silberschatz, A., Galvin, P., Gagne, G.: Applied Operating System Concepts. John Wiley & Sons, Inc., Chichester (2000)Google Scholar
  24. 24.
    Slock, P., Wuytack, S., Catthoor, F., de Jong, G.: Fast and extensive system-level memory exploration for ATM applications. In: Proc. the 10th ACM/IEEE International Symposium on System Level Synthesis, September 1997, pp. 74–81 (1997)Google Scholar
  25. 25.
    Stoutamire, D.: Portable, modular expression of locality. Ph.D. Thesis, University of California at Berkeley, CA (1997)Google Scholar
  26. 26.
    Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Kim, H.Y., Ye, W.: Energy-driven integrated hardware-software optimizations using Simple Power. In: Proc. the International Symposium on Computer Architecture (June 2000)Google Scholar
  27. 27.
    Vo, K.-P.: Vmalloc: a general and efficient memory allocator. Software Practice & Experience 26, 1–18 (1996)CrossRefGoogle Scholar
  28. 28.
    Weinstock, C.B., Wulf, W.A.: Quickfit: an efficient algorithm for heap storage allocation. ACM Notices 23(10), 141–144 (1988)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Victor De La Luz
    • 1
  • Mahmut Kandemir
    • 1
  • Guangyu Chen
    • 1
  • Ibrahim Kolcu
    • 2
  1. 1.Department of Computer Science and EngineeringThe Pennsylvania State UniversityUniversity ParkUSA
  2. 2.Computation DepartmentUMISTManchesterUK

Personalised recommendations