Capacitor-on-Metal/Via-Stacked-Plug (CMVP) Memory Cell Technologies and Application to a Nonvolatile SRAM

Abstract

A capacitor-on-metal/via-stacked-plug (CMVP) memory cell was developed for the 0.25 micr meter CMOS logic embedded FeRAM. Using a 445 C MOCVD Pb(Zr,Ti)O_{3}$ process, a ferroelectric capacitor is formed after CMOS logic fabrication. Thus, FeRAM can be embedded without changing any logic devices and processes. Furthermore, this technology enables cell size reduction (3.2 micro squaremeter for 1T-1C), the minimum process damage on the ferroelectric capacitor, and a low manufacturing cost. This CMVP process technology permits a nonvolatile SRAM (NV-SRAM) cell consisting of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. The READ and WRITE operations in this cell are very similar to those of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A Vdd/2 plate-line architecture makes READ/WRITE fatigue negligible.