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Chain \protect\mbox{FeRAMs}

  • Daisaburo TakashimaEmail author
  • Yukihito Oowaki
Chapter
Part of the Topics in Applied Physics book series (TAP, volume 93)

Abstract

A chain FeRAM (TM) is a solution for future high-density and high-speed nonvolatile memory. One memory cell consists of one transistor and one ferroelectric capacitor connected in parallel, and one memory cell block consists of a member of cells in series. This configuration realizes a small memory cell of 4 F\(^{2}\) size in the ideal case and a fast random access time. In this chapter, overview and design techniques for chain FeRAM are presented. Not only chain architecture but also several design techniques for realizing 1. high-speed, 2. high-density, and 3. low-voltage operation are discussed. 0.25 micro meter 8 Mb chain FeRAMs using these techniques are demonstrated.

Keywords

77.84.B 68.55.J 

Keywords

77.84.B 68.55.J 

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Authors and Affiliations

  1. 1.SoC R & D Center, Toshiba Corp., Semiconductor Company

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