Operation Principle and Circuit Design Issues

Abstract

This chapter provides an introduction to the circuit design aspects of ferroelectric random access memories (FeRAM). A FeRAM stores binary data in an array of FeRAM cells, each consisting of either two transistors and two capacitors (2T-2C cell) or one transistor and one capacitor (1T-1C cell). The 2T-2C cell stores both the binary data and its complement on the two capacitors. Compared to the 1T-1C cell, the 2T-2C cell provides data storage that is robust to process variation at the price of using twice the silicon area. The 1T-1C cell stores the binary data only, and not its complement, to save silicon area at the price of more complex data sensing. Two well-known approaches for data sensing are step sensing and pulse sensing. There are a variety of circuit architectures for FeRAMs. This chapter presents a few well-known architectures and points to the literature for the most recently proposed FeRAM architectures.