Towards Testing SDL Specifications: Models and Fault Coverage for Concurrent Timers

  • Mariusz A. Fecko
  • M. Ümit Uyar
  • Ali Y. Duale
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2767)


A recent model for testing systems with multiple timers is extended to compute proper input delays and timeout settings, and is applied to several types of timers required in a testing procedure. In the model, any transition in the specification can be made conditional on a set of running timers. Depending on the path taken to reach an edge, the values of the timer variables may render the traversal of the edge infeasible. The presented modeling technique, combined with the INconsistencies DEtection and ELimination (INDEEL) algorithms, allows the generation of feasible test sequences. The model also offers the flexibility to define timer lengths as variables, and have the INDEEL find the appropriate timer ranges. An approach to apply this new methodology to SDL timed extensions (guarding and delaying timers) is presented.


conformance testing timed EFSM timed extensions SDL 


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Copyright information

© IFIP International Federation for Information Processing 2003

Authors and Affiliations

  • Mariusz A. Fecko
    • 1
  • M. Ümit Uyar
    • 2
  • Ali Y. Duale
    • 3
  1. 1.Applied Research AreaTelcordia Technologies Inc.PiscatawayUSA
  2. 2.Electrical Engineering Dept.CCNY, The City University of New YorkUSA
  3. 3.System Architecture ComplianceIBM Corp.PoughkeepsieUSA

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