Partitioning for DSP Software Synthesis

  • Ming-Yung Ko
  • Shuvra S. Bhattacharyya
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2826)


Many modern DSP processors have the ability to access multiple memory banks in parallel. Efficient compiler techniques are needed to maximize such parallel memory operations to enhance performance. On the other hand, stringent memory capacity is also an important requirement to meet, and this complicates our ability to lay out data for parallel accesses. We examine these problems, data partitioning and minimization, jointly in the context of software synthesis from dataflow representations of DSP algorithms. Moreover, we exploit specific characteristics in such dataflow representations to streamline the data partitioning process. Based on these observations on practical dataflow-based DSP benchmarks, we develop simple, efficient partitioning algorithms that come very close to optimal solutions. Our experimental results show 19.4% average improvement over traditional coloring strategies with much higher efficiency than ILP-based optimal partitioning computation. This is especially useful during design space exploration, when many candidate synthesis solutions are being evaluated iteratively.


Data Partitioning Memory Bank Design Space Exploration Conflict Graph Register Allocation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Avissar, O., Barua, R., Stewart, D.: Heterogeneous Memory Management for Embedded Systems. In: CASES 2001, Atlanta, November 2001, pp. 34–43 (2001)Google Scholar
  2. 2.
    Barth, P.: Logic-Based 0-1 Constraint Programming. Kluwer Academic Publishers, Dordrecht (1996)zbMATHGoogle Scholar
  3. 3.
    Barua, R., Lee, W., Amarasinghe, S., Agarwal, A.: Compiler Support for scalable and Efficient Memory Systems. IEEE Transactions on Computers 50(11), 1234–1247 (2001)CrossRefGoogle Scholar
  4. 4.
    Bhattacharyya, S.S., Leupers, R., Marwedel, P.: Software synthesis and code generation for DSP. IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing 47(9), 849–875 (2000)CrossRefGoogle Scholar
  5. 5.
    Bhattacharyya, S.S., Murthy, P.K., Lee, E.A.: Software Synthesis from Dataflow Graphs. Kluwer Academic Publishers, Dordrecht (1996)zbMATHGoogle Scholar
  6. 6.
    Buck, J.T., Ha, S., Lee, E.A., Messerschmitt, D.G.: Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems. International Journal of Computer Simulation 4, 155–182 (1994)Google Scholar
  7. 7.
    Cho, J., Paek, Y., Whalley, D.: Efficient Register and Memory Assignment for Non-orthogonal Architectures via Graph coloring and MST Algorithms. In: LCTES 2002-SCOPES 2002, Berlin, June 2002, pp. 130–138 (2002)Google Scholar
  8. 8.
    Frohlich, S., Wess, B.: Integrated Approach to Optimized Code Generation for Heterogeneous-Register Architectures with Multiple Data-Memory Banks. In: Proceedings of IEEE 14th Annual ASIC/SOC Conference, Arlington, September 2001, pp. 122–126 (2001)Google Scholar
  9. 9.
    Garey, M.R., Johnson, D.S.: Computers and Intractability. W. H. Freeman, New York (1979)zbMATHGoogle Scholar
  10. 10.
    Lee, E.A., Messerschmitt, D.G.: Synchronous dataflow. Proceedings of the IEEE 75(9), 1235–1245 (1987)CrossRefGoogle Scholar
  11. 11.
    Leupers, R., Kotte, D.: Variable Partitioning for Dual Memory Bank DSPs. In: ICASSP, Salt Lake City (May 2001)Google Scholar
  12. 12.
    Panda, P.R.: Memory Bank customization and Assignment in Behavioral Synthesis. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, November 1999, pp. 477–481 (1999)Google Scholar
  13. 13.
    Panda, P.R., Catthoor, F., Dutt, N.D., et al.: Data and Memory Optimization Techniques for Embedded Systems. ACM Transactions on Design Automation for Electronic Systems 6(2), 149–206 (2001)CrossRefGoogle Scholar
  14. 14.
    Panda, P.R., Dutt, N.D., Nicolau, A.: On-Chip vs. Off-Chip Memory: The Data Partitioning Problem in Embedded Processor-Based Systems. ACM Transactions on Design Automation of Electronic Systems 5(3), 682–704 (2000)CrossRefGoogle Scholar
  15. 15.
    Powell, D.B., Lee, E.A., Newman, W.C.: Direct Synthesis of Optimized DSP Assembly Code from Signal Flow Block Diagrams. In: ICASSP 1992, March 1992, vol. 5, pp. 23–26 (1992)Google Scholar
  16. 16.
    Ritz, S., Willems, M., Meyr, H.: Scheduling for Optimum Data Memory Compaction in Block Diagram Oriented Software Synthesis. In: ICASSP 1995, May 1995, pp. 2651–2654 (1995)Google Scholar
  17. 17.
    Saghir, M.A.R., Chow, P., Lee, C.G.: Exploiting Dual Data-Memory Banks in Digital Signal Processors. In: Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996, pp. 234–243 (1996)Google Scholar
  18. 18.
    Sudarsanam, A., Malik, S.: Simultaneous Reference Allocation in Code Generation for Dual Data Memory Bank ASIPs. ACM Transactions on Design Automation of Electronic Systems 5(2), 242–264 (2000)CrossRefGoogle Scholar
  19. 19.
    Tarjan, R.E.: Depth first search and linear graph algorithms. SIAM Journal on Computing 1(2), 146–160 (1972)zbMATHCrossRefMathSciNetGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Ming-Yung Ko
    • 1
  • Shuvra S. Bhattacharyya
    • 1
  1. 1.Electrical and Computer Engineering Department, and, Institute for Advanced Computer StudiesUniversity of MarylandCollege ParkUSA

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