Partitioning for DSP Software Synthesis
Many modern DSP processors have the ability to access multiple memory banks in parallel. Efficient compiler techniques are needed to maximize such parallel memory operations to enhance performance. On the other hand, stringent memory capacity is also an important requirement to meet, and this complicates our ability to lay out data for parallel accesses. We examine these problems, data partitioning and minimization, jointly in the context of software synthesis from dataflow representations of DSP algorithms. Moreover, we exploit specific characteristics in such dataflow representations to streamline the data partitioning process. Based on these observations on practical dataflow-based DSP benchmarks, we develop simple, efficient partitioning algorithms that come very close to optimal solutions. Our experimental results show 19.4% average improvement over traditional coloring strategies with much higher efficiency than ILP-based optimal partitioning computation. This is especially useful during design space exploration, when many candidate synthesis solutions are being evaluated iteratively.
KeywordsData Partitioning Memory Bank Design Space Exploration Conflict Graph Register Allocation
Unable to display preview. Download preview PDF.
- 1.Avissar, O., Barua, R., Stewart, D.: Heterogeneous Memory Management for Embedded Systems. In: CASES 2001, Atlanta, November 2001, pp. 34–43 (2001)Google Scholar
- 6.Buck, J.T., Ha, S., Lee, E.A., Messerschmitt, D.G.: Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems. International Journal of Computer Simulation 4, 155–182 (1994)Google Scholar
- 7.Cho, J., Paek, Y., Whalley, D.: Efficient Register and Memory Assignment for Non-orthogonal Architectures via Graph coloring and MST Algorithms. In: LCTES 2002-SCOPES 2002, Berlin, June 2002, pp. 130–138 (2002)Google Scholar
- 8.Frohlich, S., Wess, B.: Integrated Approach to Optimized Code Generation for Heterogeneous-Register Architectures with Multiple Data-Memory Banks. In: Proceedings of IEEE 14th Annual ASIC/SOC Conference, Arlington, September 2001, pp. 122–126 (2001)Google Scholar
- 11.Leupers, R., Kotte, D.: Variable Partitioning for Dual Memory Bank DSPs. In: ICASSP, Salt Lake City (May 2001)Google Scholar
- 12.Panda, P.R.: Memory Bank customization and Assignment in Behavioral Synthesis. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, November 1999, pp. 477–481 (1999)Google Scholar
- 15.Powell, D.B., Lee, E.A., Newman, W.C.: Direct Synthesis of Optimized DSP Assembly Code from Signal Flow Block Diagrams. In: ICASSP 1992, March 1992, vol. 5, pp. 23–26 (1992)Google Scholar
- 16.Ritz, S., Willems, M., Meyr, H.: Scheduling for Optimum Data Memory Compaction in Block Diagram Oriented Software Synthesis. In: ICASSP 1995, May 1995, pp. 2651–2654 (1995)Google Scholar
- 17.Saghir, M.A.R., Chow, P., Lee, C.G.: Exploiting Dual Data-Memory Banks in Digital Signal Processors. In: Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996, pp. 234–243 (1996)Google Scholar