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Partitioning for DSP Software Synthesis

  • Ming-Yung Ko
  • Shuvra S. Bhattacharyya
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2826)

Abstract

Many modern DSP processors have the ability to access multiple memory banks in parallel. Efficient compiler techniques are needed to maximize such parallel memory operations to enhance performance. On the other hand, stringent memory capacity is also an important requirement to meet, and this complicates our ability to lay out data for parallel accesses. We examine these problems, data partitioning and minimization, jointly in the context of software synthesis from dataflow representations of DSP algorithms. Moreover, we exploit specific characteristics in such dataflow representations to streamline the data partitioning process. Based on these observations on practical dataflow-based DSP benchmarks, we develop simple, efficient partitioning algorithms that come very close to optimal solutions. Our experimental results show 19.4% average improvement over traditional coloring strategies with much higher efficiency than ILP-based optimal partitioning computation. This is especially useful during design space exploration, when many candidate synthesis solutions are being evaluated iteratively.

Keywords

Data Partitioning Memory Bank Design Space Exploration Conflict Graph Register Allocation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Ming-Yung Ko
    • 1
  • Shuvra S. Bhattacharyya
    • 1
  1. 1.Electrical and Computer Engineering Department, and, Institute for Advanced Computer StudiesUniversity of MarylandCollege ParkUSA

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