Advertisement

Retargetable Graph-Coloring Register Allocation for Irregular Architectures

  • Johan Runeson
  • Sven-Olof Nyström
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2826)

Abstract

Global register allocation is one of the most important optimizations in a compiler. Since the early 80’s, register allocation by graph coloring has been the dominant approach. The traditional formulation of graph-coloring register allocation implicitly assumes a single bank of non-overlapping general-purpose registers and does not handle irregular architectural features like overlapping register pairs, special purpose registers, and multiple register banks. We present a generalization of graph-coloring register allocation that can handle all such irregularities. The algorithm is parameterized on a formal target description, allowing fully automatic retargeting. We report on experiments conducted with a prototype implementation in a framework based on a commercial compiler.

Keywords

Target Model Graph Coloring Runtime System Benchmark Suite Local Colorability 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 2nd edn. Morgan Kaufmann Publishers, San Francisco (1996)zbMATHGoogle Scholar
  2. 2.
    Chaitin, G.J., Auslander, M.A., Chandra, A.K., Cocke, J., Hopkins, M.E., Markstein, P.W.: Register allocation via coloring. Computer Languages 6, 47–57 (1981)CrossRefGoogle Scholar
  3. 3.
    Appel, A.W.: Modern Compiler Implementation in ML. Cambridge University Press, Cambridge (1998)Google Scholar
  4. 4.
    Morgan, R.: Building an Optimizing Compiler. Digital Press (1998)Google Scholar
  5. 5.
    Muchnick, S.S.: Advanced Compiler Design and Implementation. Morgan Kaufmann, San Francisco (1997)Google Scholar
  6. 6.
    Briggs, P.: Register allocation via graph coloring. PhD thesis, Rice University (1992)Google Scholar
  7. 7.
    George, L., Appel, A.W.: Iterated register coalescing. In: TOPLAS, vol. 18, pp. 300–324 (1996)Google Scholar
  8. 8.
    Runeson, J., Nyström, S.O.: Generalizing Chaitin’s algorithm: Graph-coloring register allocation for irregular architectures. Technical Report 021, Departmentof Information Technology, Uppsala University, Sweden (2002)Google Scholar
  9. 9.
    Ramsey, N., Davidson, J.W.: Machine descriptions to build tools for embedded systems. In: Müller, F., Bestavros, A. (eds.) LCTES 1998. LNCS, vol. 1474, pp. 176–188. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  10. 10.
    Bradlee, D.G., Henry, R.R., Eggers, S.J.: The Marion system for retargetable instruction scheduling. In: PLDI (1991)Google Scholar
  11. 11.
    IAR Systems: EWARM (2003), http://www.iar.com/Products/?name=EWARM
  12. 12.
    Jagger, D., Seal, D.: ARM Architecture Reference Manual, 2nd edn. Addison-Wesley, Reading (2000)Google Scholar
  13. 13.
    Fraser, C.W., Hanson, D.R.: Simple register spilling in a retargetable compiler. Software - Practice and Experience 22, 85–99 (1992)CrossRefGoogle Scholar
  14. 14.
    Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: A free, commercially representative embedded benchmark suite. In: IEEE 4th Annual Workshop on Workload Characterization (2001)Google Scholar
  15. 15.
    Engblom, J.: Why SpecInt95 should not be used to benchmark embedded systemstools. In: LCTES. ACM Press, New York (1999)Google Scholar
  16. 16.
    Smith, M.D., Holloway, G.: Graph-coloring register allocation for architectures with irregular register resources. (unpublished manuscript) (2001), http://www.eecs.harvard.edu/machsuif/publications/publications.html
  17. 17.
    Scholz, B., Eckstein, E.: Register allocation for irregular architectures. In: LCTES-SCOPES. ACM Press, New York (2002)Google Scholar
  18. 18.
    Kong, T., Wilken, K.D.: Precise register allocation for irregular register architectures. In: Proc. Int’l Symp. on Microarchitecture (1998)Google Scholar
  19. 19.
    Appel, A.W., George, L.: Optimal spilling for CISC machines with few registers. In: PLDI (2001)Google Scholar
  20. 20.
    Marwedel, P., Goosens, G.: Code Generation for Embedded Processors. Kluwer, Dordrecht (1995)Google Scholar
  21. 21.
    Bashford, S., Leupers, R.: Phase-coupled mapping of data flow graphs to irregular data paths. In: Design Automation for Embedded Systems, vol. 4, pp. 1–50. Kluwer Academic Publishers, Dordrecht (1999)Google Scholar
  22. 22.
    Kessler, C., Bednarski, A.: Optimal integrated code generation for clustered VLIW architectures. In: LCTES, pp. 102–111. ACM Press, New York (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Johan Runeson
    • 1
  • Sven-Olof Nyström
    • 1
  1. 1.Department of Information TechnologyUppsala University 

Personalised recommendations