Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation
To cope with the highly complex and irregular embedded processor architectures, we employ the two traditionally-known most aggressive and computationally expensive code generation methods. One is integrated code generation where two main subproblems of code generation, instruction selection and register allocation, are simultaneously solved. The other is directed acyclic graph (DAG) covering, not tree covering, for code generation. In principle, unifying these two expensive methods may increase compilation time prohibitively. However often in practice, we have observed that the overall time can be manageably short without degrading the code quality by adding a few heuristics that fully capitalize on specific characteristics of target processor models.
KeywordsCompilation Time Register Allocation Register Class Embed Processor Target Machine
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