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Optimized RISC Architecture for Multiple-Precision Modular Arithmetic

  • Johann Großschädl
  • Guy-Armand Kamendje
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2802)

Abstract

Public-key cryptosystems normally spend most of their execution time in a small fraction of the program code, typically in an inner loop. The performance of these critical code sections can be significantly improved by customizing the processor’s instruction set and microarchitecture, respectively. This paper shows the advantages of instruction set extensions to accelerate the processing of cryptographic workloads such as long integer modular arithmetic. We define two custom instructions for performing multiply-and-add operations on unsigned integers (single-precision words). Both instructions can be efficiently executed by a (32 × 32 + 32 + 32)-bitmultiply/accumulate (MAC) unit. Thus, the proposed extensions are simple to integrate into standard 32-bitRISC cores like the MIPS32 4Km. We present an optimized Assembly routine for fast multiple-precision multiplication with ”finely” integrated Montgomery reduction (FIOS method). Simulation results demonstrate that the custom instructions double the processor’s arithmetic performance compared to a standard MIPS32 core.

Keywords

RSA Algorithm Montgomery Multiplication Finely IntegratedOperand Scanning (FIOS) Multi-Application Smart Cards 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Johann Großschädl
    • 1
  • Guy-Armand Kamendje
    • 1
  1. 1.Institute for Applied Information Processing and CommunicationsGraz University of TechnologyGrazAustria

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